Bus bridge and method for ordering read and write operations in

Details Bus bridge and method for ordering read and write operations in Bus bridge and method for ordering read and write operations in

1998-11-24

2000-12-05

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, 711141, 370402, G06F 1300, G06F 1200

Patent

active

061579777

ABSTRACT:
A bus bridge is disclosed that provides an interface between two computer buses and guarantees the proper ordering of write operations mastered from one bus relative to read operations mastered from the other bus where the presence of write posting storage in the bus bridge could cause ordering violations. The bus bridge includes a first mechanism for counting the number of write operations that are received by the bus bridge and queued in the write posting storage. In addition, the bus bridge includes a second mechanism for counting the number of write operations completed on the second bus. A mechanism for measuring the age of data held in each cache line of a coherent cache is also included as part of the bus bridge. Finally, the bus bridge includes a mechanism for delaying the completion of a read operation from the cache until all writes that were accepted by the bus bridge on the first bus before the cache data was fetched have been completed on the second bus. This is determined by comparing the age of the data held in a cache line to be read with the difference between the number of write operations received by the bus bridge and the number of write operations that have completed on the second bus.

REFERENCES:
patent: 5613075 (1997-03-01), Wade et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5881253 (1999-03-01), Seeman
patent: 5918069 (1999-06-01), Matoba

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