Bus bridge and data transfer method

Details Bus bridge and data transfer method Bus bridge and data transfer method

2007-08-28

2007-08-28

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S060000, C710S310000

Reexamination Certificate

active

11064084

ABSTRACT:
In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.

REFERENCES:
patent: 5761450 (1998-06-01), Shah
patent: 5764966 (1998-06-01), Mote, Jr.
patent: 10-4420 (1998-01-01), None
patent: 11-110342 (1999-04-01), None
patent: 2001-109706 (2001-04-01), None

Affiliated with

Also associated with

Rating

Bus bridge and data transfer method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus bridge and data transfer method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus bridge and data transfer method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3894480