Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2003-06-04
2004-11-30
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S240000, C370S438000
Reexamination Certificate
active
06826640
ABSTRACT:
TECHNICAL FIELD
This invention relates to bus bandwidth control.
BACKGROUND
A wide variety of devices produce data that needs to be processed and put onto networks such as the internet or a local intranet. These devices often require a computer system that issues control signals, collects data, and has the capability to put the data onto networks. A System On a Chip (SOC) can be such a computer system. These devices include embedded real-time system products such as color-printers, network enabled projectors, and surveillance cameras with different data bandwidth requirements. This category of devices also includes imaging-specific solutions for offices such as network-enabling printers, digital copiers, multifunction devices (MFDs), faxes, and scanners. Typically, these devices in a single location (such as in an office) share a system bus with a finite bandwidth to communicate with a single computer system. The finite bandwidth of the system bus is shared between the devices with different data bandwidth requirements. These devices plug into the computer system's input/output (I/O) ports and these I/O ports connect with a central processing unit (CPU) of the computer system via the system bus. Typically, these I/O ports and CPU have data buffers that store data to be transferred to somewhere else on the system bus until the system bus is ready to transfer the data.
The I/O ports and the CPU are independent bus masters because each I/O port or CPU can independently transfer data from itself across the system bus to some other I/O or CPU. Such system buses with independent bus masters typically use bus arbitration that arbitrates between different bus masters that are simultaneously waiting to transfer data on the bus. The bus masters signal that they need to transfer data by sending data transfer request signals to the bus arbitration system. Typically, in one data transfer cycle, bus arbitration has some schema to select one bus master from a set of bus masters waiting to transfer data and grants bus access to the selected bus master to transfer a packet of data. In some examples, the size of this data packet relates to the number of parallel data lines in the bus. Thus, if the bus has 32 data lines, for example, the data packet is 32 bits. This cycle is repeated.
SUMMARY
In one aspect, the invention features a system that includes a central processing unit (CPU), one or more input/output (I/O) ports designed to connect with external devices, a data bus connecting the CPU with the I/O ports, bus request and grant channels, and a bus arbiter that executes a repetitive series of the positive number of cycles, where for each cycle, for each of the bus request and grant channels that is assigned to a bus master and that has a weight equal or greater than a number of cycles already executed, if the bus master assigned to the bus request and grant channel has data waiting to be transferred on the bus then the bus arbiter grants the bus master to transfer a data packet from the data using the data bus.
Embodiments of the system may include one or more of the following. A first register configured by the CPU with which bus master can be assigned to each respective bus request and grant channel. A second register configured by the CPU with the weight that can be assigned to each bus request and grant channel assigned to a respective bus master. A third register configured to store which bus master has data waiting to be transferred on the bus. The data bus conveys data between the CPU and the input/output (I/O) ports connected to peripheral devices. The CPU, the bus arbiter, the data bus, and the I/O ports are part of a system on a chip (SOC). There are twice as many bus request and grant channels as bus masters. The number of bus request and grant channels assigned to a bus master can be dependent on bus bandwidth requirements of the bus master.
In another aspect, the invention features a method. The method includes enabling an assignment of each bus master from a plurality of bus masters to one or more bus request and grant channels not already assigned to a bus master, enabling an assignment of a weight from one to a positive number greater than one to each bus request and grant channel that is assigned to a bus master, and for a repetitive series of the positive number of cycles, for each of the bus request and grant channels that are assigned to a corresponding bus master, that has a weight equal or greater than a number of cycles already executed, if the bus master assigned to the bus request and grant channel has data waiting to be transferred on the bus then granting bus access to the bus master to transfer a data packet from the data using a data bus.
Embodiments of the method may include one or more of the following. Storing which bus master can be assigned to each respective bus request and grant channel in a first register. Storing the weight that can be assigned to each bus request and grant channel assigned to a respective bus master in a second register. Storing each of the bus masters assigned to bus request and grant channels that has data waiting to be transferred in a third register. The data bus conveys data between a central processing unit (CPU) and input/output (I/O) ports connected to peripheral devices. The CPU, a bus arbiter, the data bus, and I/O ports are part of a system on a chip (SOC). There are twice as many bus request and grant channels as bus masters. The number of bus request and grant channels assigned to a bus master can be dependent on bus bandwidth requirements of the bus master.
These and other embodiments can have one or more of the following advantages. A bus bandwidth control system allows users to flexibly allocate system bus bandwidth based on the actual needs of each individual functional module within a particular application, under worst-case operating condition. This flexibility allows a computer system with the bus bandwidth control system to fit many applications as long as the total bus bandwidth requirements do not exceed the bus bandwidth capacity of the computer system. These different applications might have different numbers of functional modules sharing the data bus with different individual bus bandwidth requirements. This capability also protects the product from being over-designed to provide full bus bandwidth for all functions at all times under worst-case conditions, thus, minimizes the final computer system cost. When, at times, a peripheral device does not require system bus access, other active modules use the allocated bus bandwidth at that time for increased performance. The bus bandwidth control system guarantees each module the required access to system resources, such as system memory, so that real-time applications never face under-run or over-run situation. Thus, this bus bandwidth control system ensures the quality and reliability of the final system.
Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
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“Performance model for a prioritized multiple-bus multiprocessor system” by John, L.K; Yu-Cheng Liu (abstract only) Publication Date: May 1996.*
“Performance model for a prioritized multiple-bus multiprocessor system” by Kurian, L; Yu-Cheng Liu (abstract only) Publication Date: Oct. 26-29, 1994.*
Eureka Technology, EC300 PCI Bus Arbiter product summary (2 pages) ©2000 by Eureka Technology Inc., http://www.eurekatech.com.
Digi International Inc.
Fish & Richardson P.C.
Ray Gopal C.
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