Bus architecture with primary bus and secondary or slave bus...

Details Bus architecture with primary bus and secondary or slave bus... Bus architecture with primary bus and secondary or slave bus...

2007-04-10

2007-04-10

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S022000, C710S052000, C710S063000, C710S306000, C710S308000, C710S309000

Reexamination Certificate

active

10744700

ABSTRACT:
A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.

REFERENCES:
patent: 5379382 (1995-01-01), Work et al.
patent: 5862387 (1999-01-01), Songer et al.
patent: 5941968 (1999-08-01), Mergard et al.
patent: 6775732 (2004-08-01), Jahnke et al.
patent: 6959354 (2005-10-01), Watanabe
patent: 1231540 (2002-08-01), None
82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4), Intel Corporation, Apr. 1997, pp. 1-284.

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