Bus architecture using debug packets to monitor transactions...

Details Bus architecture using debug packets to monitor transactions... Bus architecture using debug packets to monitor transactions...

2006-09-12

2006-09-12

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S040000, C714S044000, C714S025000

Reexamination Certificate

active

07107494

ABSTRACT:
A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, and the N peripheral devices. The communication bus comprises debug circuitry for capturing bus transaction data associated with a bus transaction between a first of the peripheral devices and a second of the peripheral devices and transferring the captured bus transaction data to an external test device.

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