Bus arbitration system with changing arbitration rules

Details Bus arbitration system with changing arbitration rules Bus arbitration system with changing arbitration rules

1999-05-18

2003-01-07

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S107000, C710S036000, C710S241000

Reexamination Certificate

active

06505265

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a bus arbitration system for arbitrating among bus requests from a plurality of bus masters in a computing device.
Many computing devices have a bus that is shared by a plurality of bus masters, typically including at least a central processing unit and a direct memory access controller. Each bus master can request the right to use the bus by sending a request signal to a bus controller. A known method of arbitrating among competing requests, employed in many conventional bus controllers, is to assign a priority order to the bus masters and grant the right to use the bus to the highest-priority bus master requesting it.
A problem with this conventional method is that it is unfair. A high-priority bus master can monopolize the bus by issuing bus requests continuously, forcing a lower-priority bus master to wait for a long time before receiving the use of the bus.
A further problem is that this method is inflexible. In many computing systems, the processes performed by the different bus masters have different levels of urgency at different times, but the conventional method employs the same priority order at all times.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to arbitrate fairly among competing requests for the use of a shared bus.
Another object is to arbitrate flexibly among competing requests for the use of a shared bus.
The invention pertains to a bus arbitration system in which a plurality of bus masters request the use of a shared bus. All aspects of the invention provide predetermined rules for arbitrating among competing requests, and change these rules at certain times, or under certain conditions.
In one aspect of the invention, a plurality of priority orders are stored in a priority-order memory. Each stored priority order assigns relative priorities to the bus masters. A priority-order selector generates a selection signal that periodically selects different stored priority orders. A bus arbiter arbitrates among competing requests from the bus masters according to the priority order currently selected by the selection signal.
This bus arbitration system can be made fair by cyclically rotating the priorities of the bus masters. It can be made flexible by storing different combinations of priority orders in the priority-order memory, responsive to different system operating conditions.
In another aspect of the invention, a request signal masking unit masks requests from a particular bus master for a certain interval each time that bus master is granted the use of the shared bus. This bus arbitration system is flexible in that the length of the interval is programmable.
In yet another aspect of the invention, one of the bus masters is a central processing unit that receives an interrupt signal. While the central processing unit is processing an interrupt, requests from other bus masters are masked for an interval of predetermined length. Preferably, the masking starts each time the use of the shared bus is granted to another bus master while the central processing unit is processing the interrupt. This bus arbitration system is also flexible in that the length of the interval is programmable.
In still another aspect of the invention, arbitration among requests for the use of the shared bus is carried out according to a priority order assigning a priority to each bus master, and requests from a particular bus master are monitored. If a request from this bus master is left unacknowledged for a certain interval, the priority of this bus master is raised. This bus arbitration system is also flexible in that the length of the interval is programmable.
In a further aspect of the invention, one of the bus masters is a central processing unit, and another one of the bus masters carries out a certain operation requiring use of the shared bus. While this operation is being carried out, bus requests from the central processing unit are ignored. The ignoring of requests may be temporarily suspended while the central processing unit is processing an interrupt. This bus arbitration system is flexible because it alters the bus arbitration rules according to special circumstances.


REFERENCES:
patent: 5253347 (1993-10-01), Bagnoli et al.
patent: 5471590 (1995-11-01), Melo et al.
patent: 5544332 (1996-08-01), Chen
patent: 5621897 (1997-04-01), Boury et al.
patent: 5796968 (1998-08-01), Takamiya
patent: 5797020 (1998-08-01), Bonella et al.

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