Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-09-28
2004-10-26
Lefkowitz, Sumati (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S033000, C710S241000
Reexamination Certificate
active
06810455
ABSTRACT:
TECHNICAL FIELD
The present invention relates to bus arbitration systems, and more particularly to a bus arbitration system using dedicated bus request and bus grant lines for bus masters.
BACKGROUND ART
In digital computer systems having a plurality of modules, such as processor modules, controller modules, communications interface or relay modules, etc., a medium is employed whereby these modules can transfer data among each other. Typically, the medium employed is a physical data channel known as a bus. The bus is connected to a communications port on each module. Each module is a potential bus master that needs the bus to communicate with other modules. It is possible that more than one potential bus master may request to use the bus simultaneously; therefore, there must be a bus arbiter to choose a winning bus master for bus grant. When the winning bus master finishes using the bus, the bus arbiter chooses the next winner, and so on. There are several well known bus allocation (arbitration) policies: fixed priority, rotating priority, round robin, least recently used policy, and first come first served scheme.
One of the most well known bus arbitration systems is the typical centralized bus arbiter with independent (dedicated) bus request and bus grant lines as shown in FIG.
1
. Each potential bus master
105
has an independent bus request line
115
connected to a centralized bus arbiter
100
and an independent bus grant line
120
coming from centralized bus arbiter
100
. A bus busy line
130
is shared by all potential bus masters
105
. All bus masters
105
have interfaces with a bus
110
. The protocol of allocating bus
110
is as follows: Master
i
105
(i=1,2, . . . , or n) requests access to bus
110
by activating its dedicated bus request line BR
i
115
. If bus busy line
130
is active indicating bus
110
is busy, i.e., being used by a bus master
105
, Master
i
keeps activating its dedicated bus request line BR
i
until it is granted access to bus
110
. This can be done by pulling low bus request line BR
i
if bus request signal on bus request line BR
i
is active low.
If bus busy line
130
is passive, i.e., no master is using bus
110
, centralized bus arbiter
100
immediately allocates bus
110
to Master
i
by activating Master
i
's dedicated grant line BG
i
120
. Master
i
then deactivates its request line BR
i
and activates bus busy line
130
. When Master
i
finishes using bus
110
, Master
i
deactivates bus busy line
130
so that centralized bus arbiter
100
knows that it can select another winning bus master
105
for bus grant.
When bus busy line
130
is active, centralized bus arbiter
100
does not accept any bus requests. When several request lines are active when bus busy line
130
becomes passive, centralized bus arbiter
100
can use any of the bus allocation policies mentioned above to choose a winner among the requesting bus masters
105
.
Although the centralized bus arbiter with independent bus request and bus grant lines in
FIG. 1
has faster arbitration time compared with daisy-chained arbiters, it requires a large number of bus arbitration lines (bus request lines, bus grant lines, bus busy lines). Therefore, it is an object of the present invention to propose a bus arbitration system and method that require fewer bus arbitration lines to implement the centralized bus arbiter with independent bus request and bus grant lines.
SUMMARY OF THE INVENTION
The bus arbitration system and method of the present invention achieve the stated object by assuming that each operation using the bus takes from one to five bus clock cycles. Each potential bus master has its dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the potential bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policy. If a potential bus master is chosen to be the winning bus master, the centralized bus arbiter activates the winning bus master's dedicated bus grant line for the same number of bus clock cycles as requested by the bus master, i.e. for three bus clock cycles. So, the bus master will have sufficient use of the bus for its desired operation. After that, the arbiter chooses the next winning bus master and activates its dedicated grant line in the same manner as described above, and so on. No bus busy line is needed in the bus arbitration system of the present invention.
REFERENCES:
patent: 5111424 (1992-05-01), Donaldson et al.
patent: 5276887 (1994-01-01), Haynie
patent: 5426740 (1995-06-01), Bennett
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5473762 (1995-12-01), Krein et al.
patent: 5528764 (1996-06-01), Heil
patent: 5611058 (1997-03-01), Moore et al.
patent: 5774455 (1998-06-01), Kawase et al.
patent: 5898694 (1999-04-01), Ilyadis et al.
patent: 6425032 (2002-07-01), Prasanna
Cradle Technologies, Inc.
Lefkowitz Sumati
Schneck Thomas
Schneck & Schneck
Vu Trisha
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