Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2005-05-17
2005-05-17
Vo, Tim (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S111000, C710S116000
Reexamination Certificate
active
06895459
ABSTRACT:
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.
REFERENCES:
patent: 4276594 (1981-06-01), Morley
patent: 4326249 (1982-04-01), Godsey
patent: 4381542 (1983-04-01), Binder et al.
patent: 4639910 (1987-01-01), Toegel et al.
patent: 4698753 (1987-10-01), Hubbins et al.
patent: 4914580 (1990-04-01), Jensen et al.
patent: 4994960 (1991-02-01), Tuchler et al.
patent: 5072365 (1991-12-01), Burgess et al.
patent: 5278974 (1994-01-01), Lemmon et al.
patent: 5467295 (1995-11-01), Young et al.
patent: 5519837 (1996-05-01), Tran
patent: 5539882 (1996-07-01), Gopal et al.
patent: 5564062 (1996-10-01), Meaney et al.
patent: 5572686 (1996-11-01), Nunziata et al.
patent: 5627976 (1997-05-01), McFarland et al.
patent: 5634004 (1997-05-01), Gopinath et al.
patent: 5649209 (1997-07-01), Umetsu et al.
patent: 5649233 (1997-07-01), Chen
patent: 5729702 (1998-03-01), Creedon et al.
patent: 5734848 (1998-03-01), Gates et al.
patent: 5832278 (1998-11-01), Pham
patent: 5845096 (1998-12-01), Munguia et al.
patent: 5909559 (1999-06-01), So
patent: 5931931 (1999-08-01), Nguyen
patent: 5987549 (1999-11-01), Hagersten et al.
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6026461 (2000-02-01), Baxter et al.
patent: 6038630 (2000-03-01), Foster et al.
patent: 6047349 (2000-04-01), Klein
patent: 6061361 (2000-05-01), An et al.
patent: 6070205 (2000-05-01), Kato et al.
patent: 6073132 (2000-06-01), Gehman
patent: 6311249 (2001-10-01), Min et al.
patent: 6347294 (2002-02-01), Booker
patent: 6389493 (2002-05-01), Barkley et al.
patent: 6401154 (2002-06-01), Chiu et al.
patent: 6470407 (2002-10-01), Losi
patent: 6496740 (2002-12-01), Robertson et al.
patent: 0426413 (1991-05-01), None
patent: 0702307 (1996-03-01), None
patent: 09424623 (1999-06-01), None
patent: WO 9926155 (1999-05-01), None
Morris Mano, “Computer System Architecture”, 1982, Prentice-Hall, Inc., vol. 2, pp434-440.*
Lou R. Rohan and Douglas R. Taube, “Weighted Round-Robin Scheduling Module”, Washington University in Saint Louis, http://www.arl.wustl.edu/˜lockwood/class/cs535/project/fairqueue.
Birk Palle
Hadwiger Rainer R.
Krivacek Paul D.
Sørensen Jørn
King Justin I.
Vo Tim
LandOfFree
Bus arbitration method employing a table of slots suitably... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bus arbitration method employing a table of slots suitably..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus arbitration method employing a table of slots suitably... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3444799