Bus arbiter operable as a DRAM controller

Details Bus arbiter operable as a DRAM controller Bus arbiter operable as a DRAM controller

1997-12-22

2000-05-30

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 22, 710 26, 710 28, 710240, 711106, G06F 1300

Patent

active

060702125

ABSTRACT:
A bus arbiter capable of avoiding needless increase in circuit scale is provided. The bus arbiter controls a bus shared by a CPU (central processing unit) and a plurality of apparatuses for generating addresses. The bus arbiter includes a determination unit for determining if a request of an address is a request of an address where no corresponding device is present, and a processor for passing the request by transmitting an ACK signal without performing a writing operation for a request of a writing operation, and transmitting dummy data and an ACK signal without performing a reading operation for a request of a reading operation, when the determination unit has determined that the request is a request of an address where no corresponding device is present.

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"Bus Request Update Mechanism to Improve Processor Performance", IBM Technical Procedure Billetin, vol. 38, No. 8, Aug. 1, 1995, pp. 261-263.

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