Bus arbiter

Details Bus arbiter Bus arbiter

2000-04-19

2003-03-04

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S036000, C710S240000

Reexamination Certificate

active

06529981

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus arbiter.
2. Description of the Related Art
In a first example of a conventional bus arbiter, since the bus arbiter does not normally operate for a request to write in/read from an address for which a corresponding device is absent, an apparatus for generating an address has the function of prohibiting a request to write in/read from an address outside a set address region, for example, by referring to an address map within the system.
In a second example of a conventional bus arbiter also operating as a DRAM (dynamic random access memory) controller as shown in
FIG. 13
, the system is controlled by a CPU
300
having a data-bus width of 16 bits, and programs to be executed by the CPU
300
are stored in a ROM (read-only memory)
400
. A bus arbiter
500
also operating as a DRAM controller arbitrates accesses of the CPU
300
and a DMA (direct memory access) controller
800
to DRAM's
600
and
700
. Each of the DRAM's
600
and
700
has a capacity of 4M bits and a data bus width of 16 bits. The DRAM's
600
and
700
store upper words and lower words, respectively. The DMA controller
800
has a data bus width of 32 bits.
There are shown signals
311
-
338
between respective blocks. Reference numeral
311
represents a chip select signal ROMCS for the ROM
400
. Reference numeral
312
represents a CPU data bus CPU_D [
15
:
0
] having a bus width of 16 bits. Reference numeral
313
represents a CPU address bus CPU_A [
23
:
1
] having a bus width of 23 bits. Reference numerals
314
,
315
,
316
,
317
,
318
,
319
, and
320
represent a reset signal Reset, a system clock signal Clock, an address strobe signal AS, a read signal RD, an upper-byte write signal UWR, a lower-byte write signal LWR, and a wait signal Wait, respectively.
Reference numeral
321
represents a DRAM address bus DRAM_A [
8
:
0
] having a bus width of 9 bits. Reference numeral
322
represents an upper-word DRAM data bus DRAM_D_U [
15
:
0
] having a bus width of 16 bits. Reference numerals
323
,
324
,
325
,
326
, and
327
represent an upper-word DRAM row-address strobe signal RAS_U, an upper-word DRAM upper-byte column-address strobe signal UCAS_U, an upper-word DRAM lower-byte column-address strobe signal LCAS_U, an upper-word DRAM write signal WE_U, and an upper-word DRAM read signal OE_U, respectively.
Reference numeral
328
represents a lower-word DRAM data bus DRAM_D_L having a bus width of 16 bits. Reference numerals
329
,
330
,
331
,
332
, and
333
represent a lower-word DRAM row-address strobe signal RAS_L, a lower-word DRAM upper-byte column-address strobe signal UCAS_L, a lower-word DRAM lower-byte column-address strobe signal LCAS_L, a lower-word DRAM write signal WE_L, and a lower-word DRAM read signal OE_L, respectively.
Reference numeral
334
represents a DMA data bus DMA_D [
31
:
0
] having a bus width of 32 bits. Reference numeral
335
represents a DMA address bus DMA_A [
23
:
21
] having a bus width of 22 bits. Reference numerals
336
,
337
, and
338
represent a DMA request signal DMA_Req, a DMA direction signal DMA_Dir, and a DMA acknowledge signal DMA_Ack, respectively.
A signal CPU_A [
0
] is absent on the CPU address bus CPU_A [
23
:
1
], because the CPU
300
has the upper-byte write signal UWR and the lower-byte write signal LWR, and therefore address assignment in units of a byte is unnecessary. A signal DMA_A [
1
:
0
] is absent on the DMA address bus DMA_A [
23
:
2
], because in this case, the data width of the DMA controller
800
is 32 bits, and therefore address assignment in units of a byte and in units of a word is unnecessary. The DRAM address bus DRAM_A [
8
:
0
] comprises only 9 bits, because in this case, the row address and the column address of the DRAM each comprise 9 bits.
FIG. 14
is an address map for the units shown in FIG.
13
. The address space of the CPU
300
comprises 0H-FFFFFFH, i.e., 16 M bytes. The addresses 0H-7FFFFFH and 800000H 8FFFFFH are allocated to the ROM
400
and to the RAM's
600
and
700
, respectively. The address 900000H and the succeeding addresses are allocated to a register of the DMA controller
800
, an input/output register (not shown in FIG.
3
), and an internal register-of the CPU
300
.
The CPU
300
executes processing in accordance with a program stored in the ROM
400
, and accesses the ROM
400
by the signal ROMCS and by bits between the 22nd bit and the 1st bit on the bus CPU_A [
23
:
1
]. Accesses from the CPU
300
and the DMA controller
800
to the DRAM's
600
and
700
are performed via the bus arbiter and DRAM controller
500
.
FIG. 15
is a flowchart illustrating the operation of the bus arbiter and DRAM controller
500
during an access by the CPU
300
. If the CPU
300
accesses the region of the ROM
400
, and an access from the DMA controller
800
is absent, i.e ., if the CPU_A [
23
:
1
] indicates 0H-7FFFFFH indicating the region of the ROM, and the DMA or the DMA_Req is not asserted, as results of determination in steps S
110
and S
102
, then, in step S
103
, CAS-Before-RAS refreshing as shown in the timing chart of
FIG. 16
is performed. More specifically, the signals UCAS_U, LCAS_U, UCAS_L and LCAS_L are asserted, and then, the signals RAS_U and RAS_L are asserted.
As described above, the bus arbiter and DRAM controller
500
has a CAS-Before-RAS refreshing function. Usually, the DRAM is required to be refreshed at a frequency equal to or greater than a specified time interval. Hence, the refreshing time interval is monitored by a timer. If the next refreshing operation is not generated for a predetermined time period after a refreshing operation, a refreshing operation is performed by forcedly interrupting the operation of the CPU
300
.
Processing from step S
104
to step S
137
is an access to the RAM region. Accordingly, in step S
104
, it is determined if an address between 800000H and 8FFFFFH of the RAM region is indicated. If the result of the determination in step S
104
is affirmative, the process proceeds to step S
105
, where a signal CPU_A [
19
:
10
] is output to the bus DRAM_A [
8
:
0
] as a row address. Then, in step S
106
, the fall of a clock pulse is detected. In step S
107
, it is determined whether a signal CPU_A [
1
] is 0 or 1, i.e, whether the DRAM
600
for upper words or the DRAM
700
for lower words is to be accessed. If the DRAM
600
is to be accessed, then, in step S
108
, the signal RAS_U is asserted. If the DRAM
700
is to be accessed, the signal RAS_L is asserted.
Then, in step S
110
or step S
111
, the rise of a clock pulse is detected. Then, in step S
112
or step S
113
, it is determined whether a reading operation or a writing operation is to be performed. In the case of a reading operation, the signal OE_U is asserted in step S
116
in the case of an upper word, and the signal OE_L is asserted in step S
117
in the case of a lower word.
In the case of a writing operation, the signal WE_L is asserted in step S
116
in the case of an upper word, and the signal WE_L is asserted in step S
117
in the case of a lower word. Then, in step S
118
or step S
119
, a signal CPU_A [
9
:
2
] is output to the bus DRAM_A [
8
:
0
] as a column address.
Then, in step S
120
or S
121
, the rise of a clock pulse is detected. In step S
122
or step S
123
, it is determined if a reading operation is to be performed. In the case of a reading operation, the signal UCAS_U or LCAS_U is asserted in step S
124
in the case of an upper word, and the signal UCAS_L or LCAS_L is asserted in step S
125
in the case of a lower word.
If a reading operation is not be performed, then, in step S
126
or S
127
, it is determined if an operation to write an upper byte is to be performed. In the case of an operation to write an upper byte, the signal UCAS_U is asserted in step S
128
in the c

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