Bus analyzer unit with programmable trace buffers

Details Bus analyzer unit with programmable trace buffers Bus analyzer unit with programmable trace buffers

2005-06-28

2005-06-28

Bonzo, Bryce P. (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S045000

Reexamination Certificate

active

06912673

ABSTRACT:
A Bus Analyzer Unit (BAU) for performing trace analysis on either or both the global bus (GBus) or the I/O bus of a semiconductor chip. The BAU has a GBus trace unit and an I/O bus trace unit, each with its own trace logic. Each unit has filters and comparators which determine what data is recorded and when it is recorded. Trace data recorded by the units is written to a programmable, circular trace buffer in local memory or an SDRAM. Each trace unit has two registers holding the start and end addresses of the trace buffer. Each unit has a next address register containing the next address to which data may be written. As data is written, the next address register is incremented. When the next address register equals the value in the end address register, the next address register is reloaded with the address in the start register.

REFERENCES:
patent: 5884023 (1999-03-01), Swoboda et al.
patent: 5887167 (1999-03-01), Sutton
patent: 5944841 (1999-08-01), Christie
patent: 6732307 (2004-05-01), Edwards
patent: 2002/0010882 (2002-01-01), Yamashita

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