Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-10-02
2007-10-02
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S189070, C711S103000, C711S005000
Reexamination Certificate
active
11353573
ABSTRACT:
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data written to a group of columns during a burst write operation. The burst columns are generated using an internal counter and an externally provided start address. Repeating sequences of commands and data packets are provided to the memory device. An externally provided data mask signal is used to write one of the data packets to the memory on each of the sequences.
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Bataille Pierre-Michel
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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