Burst transfer register arrangement

Electrical computers and digital data processing systems: input/ – Input/output data processing – Transfer termination

Reexamination Certificate

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C710S032000

Reexamination Certificate

active

10728677

ABSTRACT:
Machine-readable media, methods, and apparatus are described to burst write a command and its arguments to control registers of a device and to burst read status and outputs of the command from control registers of the device. During the burst write, the arguments may be transferred to the device in a reverse order in which the last argument is transferred first and the first argument is transferred last. Further, the command may be transferred after the arguments.

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Video Electronics Standards Assoc. (VESA), “Display Data Channel Command Interface (DDC/CI) Standard”, Version 1, Aug. 14, 1998, 43 pages.
Video Electronics Standards Assoc. (VESA), “Enhanced Display Data Channel Standard”, Version 1, Sep. 2, 1999, 21 pages.
Video Electronics Standards Assoc. (VESA), “VESA Monitor Control Command Set (MCCS) Standard”, Version 2, Oct. 17, 2003, 42 pages.

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