Burst transfer memory

Details Burst transfer memory Burst transfer memory

2005-08-02

2005-08-02

Vital, Pierre M. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S005000, C345S537000, C365S230090

Reexamination Certificate

active

06925543

ABSTRACT:
The present invention provides a burst transfer memory comprising a first memory having a cell array arranged in a matrix, a second memory which has a cell array arranged in a matrix and which performs a random access operation at a higher speed than the first memory, and an interface circuit which controls the first and second memories as one burst transfer memory, and wherein the interface circuit allocates addresses to the first and second memories as consecutive addresses, and the interface circuit substantially simultaneously starts the first random access to the first and second memories, accesses the second memory before a word line of the first memory is activated, and consecutively accesses a page of the first memory after the word line of the first memory has been activated.

REFERENCES:
patent: 5703822 (1997-12-01), Ikeda
patent: 5953244 (1999-09-01), Okada et al.
patent: 6151268 (2000-11-01), Yoshikawa

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