Burst SRAMs for use with a high speed clock

Details Burst SRAMs for use with a high speed clock Burst SRAMs for use with a high speed clock

1997-02-14

1998-09-15

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

395556, 395559, G06F 1328

Patent

active

058095497

ABSTRACT:
Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

REFERENCES:
patent: 4618947 (1986-10-01), Tran et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5587954 (1996-12-01), Vogley et al.

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