Burst signal generation for pipelined access to AMBA bus

Details Burst signal generation for pipelined access to AMBA bus Burst signal generation for pipelined access to AMBA bus

2001-05-09

2003-12-02

Tung, Kee M. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Logical operations

C345S572000

Reexamination Certificate

active

06657636

ABSTRACT:

This application claims the benefit of United Kingdom Application No. 0100965.3 filed Jan. 13, 2001.
FIELD OF THE INVENTION
The present invention relates to the generation of burst data transfers generally, and, more particularly to burst data transfers using an Advanced RISC Microcontrolled Bus Architecture (AMBA) AHB bus.
BACKGROUND OF THE INVENTION
A bus is a signal route formed by a set of parallel conductors to which various items of a computer system may be connected in parallel, such that information can be transferred. The signals on the bus can be of a particular type (i.e., on a data bus or an address bus). Additionally, the signals on a bus can be intermixed. A number of widely used proprietary bus systems currently exist (i.e., the AMBA AHB bus by Advanced Risc Machines (ARM)). The AMBA AHB can be used for connecting a data processing block such as a graphics block move engine (BME) or video decoder and an area of memory.
Various dynamic memory types are used in computers, (i.e., DRAM, SDRAM, DDRDRAM, etc.). The memories transfer data to/from a data processing block in bursts of data. However, bursts of data on the AHB bus can only be used under the following conditions.
1. For high performance access to dynamic memory, each burst of data must include a fixed number of data word transfers (or beats). The fixed number being a mathematical progression of 4. Therefore, each burst of data comprises 4, 8 or 16 beats. In addition, the number of beats must be known at the start of the burst of data since unspecified length bursts cannot be implemented.
2. Full bus-width data word transfers must be used for each beat of the data burst.
3. The block of data which is read from or written to memory, which is to form the data burst must be located at consecutive, sequentially increasing addresses.
4. The sequence of consecutive addresses must not cross a 1 KB (1024 byte) word boundary.
SUMMARY OF THE INVENTION
The present invention concerns a method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory. The method comprises the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.
The objects, features and advantages of the present invention include providing a method and/or architecture for data burst transfers that may generate bursts of data at every possible opportunity for a particular situation (e.g., when a graphics or video processing device reads or writes rectangular blocks of data). Additionally, the rectangular blocks of data may be displayed on a screen in two dimensions.


REFERENCES:
patent: 5721885 (1998-02-01), Nishide
“Block transfer scheme pushes VMEbus limits” by David Lieberman, Computer Design, v27, n6, p25(2), Mar. 15, 1988.

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