Burst read circuit in semiconductor memory device and burst...

Details Burst read circuit in semiconductor memory device and burst... Burst read circuit in semiconductor memory device and burst...

2008-05-20

2008-05-20

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S233500

Reexamination Certificate

active

07376044

ABSTRACT:
A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequentially sense and amplifies data stored in the memory cell array. The latch circuit is configured for latching sensed data of the sense amplifier group and outputting the sensed data in response to a DUMP signal. The burst mode control unit is configured for detecting the length of invalid data included in the sensed data from a burst start address and controlling a point in time of DUMP signal generation according to the detection result to sequentially output only valid data among the sensed data.

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