Burst-mode DRAM

Static information storage and retrieval – Read/write circuit

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Details

36518905, 36523001, 36523003, 36523008, 365233, G11C 700

Patent

active

053922395

ABSTRACT:
A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.

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Jones et al., "Fast Dynamic RAMs," IEEE Spectrum, Oct. 1992, pp. 44-45.
"256K.times.16 DRAM Fast Page Mode," Micron Technology, Inc., 1992, pp. 2-169-2-190.

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