Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-12-09
2002-02-12
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000, C711S167000, C365S189030, C365S230080, C365S230060, C365S238500
Reexamination Certificate
active
06347356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a burst length discriminating circuit for use in a synchronous semiconductor memory with a burst mode.
2. Description of Related Art
In the prior art, a synchronous semiconductor memory circuit having a burst mode has been known.
In the prior art semiconductor memory circuit having the burst mode, as shown in
FIG. 4
, a mode discriminating circuit
100
receives various control signals including at least a row address strobe signal RAS, a column address strobe signal CAS, and an internal address (only one address signal IA
11
, of which is shown in FIG.
4
), and outputs various mode signals labeled “MODE FLAGS”. The mode discriminating circuit
100
is initialized by a power-on-reset signal PON supplied to a reset input of the mode discriminating circuit
10
.
The inputted signals are held in D-latches (not shown) during a high level period of an internal clock CLK which is brought to a high level during a predetermined period of time from a rising of an external clock. “D-latches” refers to D-type flip flops or latches. Outputs of the D-latches (not shown) are connected to a decoder (not shown) so that the outputs of the D-latches are converted by action of the decoder into mode signals in accordance with a combination of the inputted signals. Each mode signal is held in a D-latch until a rising of a next internal clock CLK.
Referring to
FIG. 5
, there is shown a logic circuit diagram of a burst length discriminating circuit included in the prior art semiconductor memory circuit having the burst mode.
FIG. 6
is a truth table of a decoder section of the burst length discriminating circuit, and
FIG. 7
is a truth table of the burst length discriminating circuit.
The shown prior art burst length discriminating circuit includes three D-latches (D-type flipflops)
1
,
2
and
3
, and a decoder
20
which is constituted of a two-input NOR gate
4
, a two-input NAND gate
5
, a three-input NOR gate
6
, a three-input NAND gate
7
and four inverters
9
,
10
,
11
and
12
, connected as shown. The D-latches (D-type flipflops)
1
,
2
and
3
latch three least significant address bits “IA
0
”, “IA
1
” and “IA
2
” of the address, in synchronism with a rising of the internal clock CLK in a mode register set cycle, and hold the latched address bits “IA
0
”, “IA
1
” and “IA
2
” until the rising of the next the internal clock CLK.
The decoder
20
selectively activates a burst length discrimination signal on the basis of the logical combination of the address bits “IA
0
”, “IA
1
” and “IA
2
”. The relation between the burst lengths and the address signals corresponding to key address signals is defined in Joint Electron Device Engineering Council (“JEDEC”) format as shown in FIG.
7
. Therefore, when all of the address bits “IA
0
”, “IA
1
” and “IA
2
” are at a high level, the burst length discrimination signal MDBLF indicating the full page burst is activated. In order to realize the truth table shown in
FIG. 7
, the decoder
20
is configured to realize the truth table shown in FIG.
6
. Namely, the truth table of the burst length discriminating circuit is the same as that of the decoder included in the burst length discriminating circuit, and therefore, the latches provided in the burst length discriminating circuit supply the decoder with the address signals having the same polarity as those applied to the burst length discriminating circuit.
At a power-on time, initial conditions of the D-latches and sequential circuits (not shown) are indefinite. Therefore, the D-latches and sequential circuits are initialized by the power-on-reset signal PON (internal initializing signal) at the power-on time, so that the semiconductor memory circuit becomes an expected predetermined internal condition.
In general, in a system such a personal computer or a work station, if a voltage is applied to an input/output pin of the semiconductor memory circuit, a minute current flows in an input protection circuit provided in the input/output pin. By utilizing this feature, just after the power-on, a bus check, in order to check whether or not a semiconductor memory circuit exists on the memory bus, is carried out by monitoring a minute current flowing when a voltage is applied to the memory bus.
In the system having the prior art semiconductor memory circuit having the burst mode, on the other hand, if the power-on-reset signal were not generated for any reason at the power-on time, the internal condition is not initialized, and the system may not return to a normal condition. As a result, if the input/output pin of the semiconductor memory circuit is in a condition of outputting the data, a large current flows, and therefore, the bus check cannot be performed.
Specifically, since the initial conditions of the D-latches and sequential circuits are indefinite at the power-on time, various internal nodes which were at the ground level at the power-on time elevate with elevation of the power supply voltage, wherein each various internal node finally becomes either the low level or the high level to which the internal node is apt to shift because of variation of an individual circuit element in a manufacturing process. As a result, the semiconductor memory circuit becomes an unexpected internal condition. However, even if the initialization results in failure, if a mode erroneously selected by the mode discriminator was a mode register setting mode, a refresh mode, or a write mode, the input/output pins are put in a high impedance condition, and therefore, no large current disadvantageously flows at the bus checking of the system.
In addition, even if the erroneously selected mode was a read mode, if the burst length selected by the burst length discriminating circuit is any of the burst lengths “1”, “2”,“4” and “8”, after the data corresponding to the designated burst length is outputted in synchronism with an external clock, the input/output pins are brought into the high impedance condition. Therefore, no substantial problem occurs.
However, if the erroneously selected mode is the read mode, and if the burst length selected by the burst length discriminating circuit is the full page (full page burst read mode), the input/output pins are maintained in a data outputting condition until a burst stop command, a precharge command or a write command (excluding the case that a CAS latency is “3”) is inputted. Namely, since the data continues to be outputted in synchronism with the external clock, a large current disadvantageously flows at the bus checking of the system.
Here, considering the burst length discriminating circuit, all the D-latches included in the burst length discriminating circuit have the same circuit construction and are formed in the same mask pattern. Therefore, at the power-on time, outputs of all the D-latches included in the burst length discriminating circuit are apt to become the same logical level which is either a high level or a low level.
Since the input-output relation of the decoder required to cause the burst length discriminating circuit to meet the relation between the key address signals and the burst lengths defined in JEDEC as shown in
FIG. 7
, is as shown in
FIG. 6
, when all the inputs of the decoder are at a high level, the full page is selected as the burst length.
In addition, in a system such as a personal computer or a work station, a memory check is carried out just after a power-on time, in order to check whether or not the semiconductor memory existing on the memory bus operates normally, by executing a reading and writing of data. In a high speed system having a plurality of semiconductor memories having the burst mode, connected to the memory bus, in parallel to one another, the plurality of semiconductor memories are checked one by one in order. In this case, not only the output pins of the semiconductor memory to be checked but also the output pins of the semiconductor memories not to be checked are connected to the s
Gossage Glenn
NEC Corporation
Young & Thompson
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