Burst error pattern generation method, and burst and byte...

Details Burst error pattern generation method, and burst and byte... Burst error pattern generation method, and burst and byte...

2006-01-24

2006-01-24

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S762000, C714S787000

Reexamination Certificate

active

06990625

ABSTRACT:
A syndrome S is found from a received information D and a parity check matrix for correcting burst errors up to b bits. The syndrome S is inputted to p sets of burst error pattern generation circuits that correspond to information frames overlapping each other by (b−1) bits and each having a length of 2b bits. If a burst error is included entirely in any one of the p sets of burst error pattern generation circuits, then the burst error pattern is outputted. An error pattern calculation circuit executes OR respectively on overlapping bits output from the error pattern generation circuits. By executing exclusive OR on an output of the error pattern calculation circuit and received information D, corrected information Dsis obtained. As a result, a burst error in the received information can be detected and corrected.

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