Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-11-15
2003-03-11
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S762000, C714S787000
Reexamination Certificate
active
06532565
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of memories. More particularly, this invention relates to burst error and additional random bit error correction in a memory.
2. Art Background
A wide variety of memory systems commonly include mechanisms for performing error correction. Error correction mechanisms typically enable the detection and correction of some types of errors that occur in stored data. The error correction mechanisms used in prior memory systems are typically based on coding schemes in which a set of error correction bits are associated with each set of stored data bits. Each set of error correction bits is usually stored together with its associated data bits to form a memory word. The bit pattern of a set of error correction bits in a memory word is usually adapted to the data bits in the memory word in a manner that enables some degree of error detection and correction when the memory word is read out of memory.
For example, one type of coding scheme commonly used for error correction in memory systems is usually referred to as two-error correcting BCH code. Typically, error correction is performed by reading a memory word from memory and using the two-error correcting BCH code to calculate a value which is commonly referred to as a syndrome. The syndrome usually indicates whether an error is present in the memory word and enables correction of up to 2 random bit errors in the memory word.
One type of error that commonly occurs in memory systems may be referred to as a burst error. A typical burst error is an error that causes the corruption of several in a series of consecutive bits in a memory word. For example, a failed address line in a memory may cause burst errors that encompass 4 consecutive bits in memory words read from the memory. Unfortunately, prior error correction mechanisms that are based on two-error correction BCH codes usually cannot correct such burst errors. Such an inability to correct burst errors usually increases the down-time and maintenance costs of systems such as computer systems, server systems, mass storage systems, and communication systems.
SUMMARY OF THE INVENTION
A system for memory word error correction is disclosed that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.
Other features and advantages of the present invention will be apparent from the detailed description that follows.
REFERENCES:
patent: 5179560 (1993-01-01), Yamagishi et al.
patent: 5642365 (1997-06-01), Murakami et al.
patent: 5657331 (1997-08-01), Metzner et al.
patent: 5943348 (1999-08-01), Ly
Blake Ian F.
Roth Ron M.
Seroussi Gadiel
Hewlett--Packard Company
Tu Christine T.
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