Burst counter controller and method in a memory device...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C365S230010, C365S004000

Reexamination Certificate

active

07003643

ABSTRACT:
A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

REFERENCES:
patent: 5077737 (1991-12-01), Leger et al.
patent: 5802005 (1998-09-01), Nakamura et al.
patent: 6091665 (2000-07-01), Dorney
patent: 6130853 (2000-10-01), Wang et al.
patent: 6240047 (2001-05-01), Koelling et al.
patent: 6278643 (2001-08-01), Penney
patent: 6310824 (2001-10-01), Schoniger et al.
patent: 6321311 (2001-11-01), Kim
patent: 6438063 (2002-08-01), Lee
patent: 6438066 (2002-08-01), Ooishi et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6473360 (2002-10-01), Ooishi
patent: 6564343 (2003-05-01), Yamashita
patent: 6618319 (2003-09-01), Ooishi et al.
patent: 6625685 (2003-09-01), Cho et al.
patent: 6629224 (2003-09-01), Suzuki et al.
patent: 6671787 (2003-12-01), Kanda et al.
patent: 6724686 (2004-04-01), Ooishi et al.
patent: 6754126 (2004-06-01), Yamaguchi et al.
patent: 6754746 (2004-06-01), Leung et al.
patent: 6762972 (2004-07-01), La
patent: 6771557 (2004-08-01), Penney
patent: 6775759 (2004-08-01), Janzen
patent: 6788597 (2004-09-01), Ladner et al.

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