Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-02-21
2006-02-21
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C365S230010, C365S004000
Reexamination Certificate
active
07003643
ABSTRACT:
A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.
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Penney Daniel B.
So Steven
Doan Duc T
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Padmanabhan Mano
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