Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1999-08-12
2002-05-21
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S011000, C710S110000
Reexamination Certificate
active
06393500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of computer system bus architectures, and more particularly to an apparatus in a bus master device for configuring the cycles in a data transfer burst to match the attributes of an addressed slave device.
2. Description of the Related Art
Computer systems have historically consisted of a number of distinct components such as a central processing unit (CPU), a memory, and input/output (I/O) logic. The CPU performs all of the computational functions, the memory stores program instructions and data that direct the CPU to perform specific functions, and the I/O logic provides an interface to devices such as video monitors, keyboards, and storage devices. The CPU must constantly transfer data to/from the memory to retrieve program instructions and to store results of computations. The CPU must also communicate with the I/O logic to retrieve commands and to display results. In many systems today, the I/O logic directly retrieves large blocks of data from the memory to allow video monitors to be refreshed without burdening the CPU.
Because the data communicated between devices in a computer system are of the same format and syntax, it is standard practice to interconnect all of the devices in a bused architecture rather than providing point-to-point connections between devices. In a bused architecture, a common set of communication signals-an address/data bus-are connected in parallel to all devices. The address signals on the address/data bus, or system bus, are used to identify a device that is the target of a data transfer. The data signals on the address/data bus are used to transfer the data to the target device. In some system configurations, the address signals and the data signals are separated, that is, separate address and data buses. In other system configurations, the address and data signals are multiplexed over the same bus by using other control signals to indicate whether an address is present on the bus or whether data are present.
Because each device in the system configuration are connected in parallel to the address/data bus, it follows then that only one instance of a data transfer can occur at any given point in time. If two devices were to execute a data transfer at the same time, then signals on the bus would be corrupted, thus precluding any transfer of data. Fortunately, system designers prescribe a set of communication rules for the bus, or bus protocol, that bars devices from transferring data at the same time. Each device connected to the bus is required to strictly adhere to the bus protocol so that simultaneous access to the bus is avoided. What this means in the integrated circuit world is that the components in a computer system are purposely designed to comply with a specific bus protocol, or perhaps to increase marketability, with a fixed set of bus protocols.
In early years, computer system buses were small, eight bits wide, the CPU was the only device that was capable of initiating a data transfer, and the number of other devices connected to the bus consisted primarily of memory and I/O logic. Accordingly, the bus protocol for such a system was very straightforward: If the CPU required a byte of data from the memory, it grabbed the bus, issued the address of the data byte to the memory, and the memory supplied the byte of data to the CPU. If more than one data byte were required, then the CPU would repeat the above process until the required number of bytes were retrieved from the memory.
But the advent of the digital computer, along with a host of associated technological advances, have completely changed the course of society over the past 20 years. Because a digital computer can be used to control a wide range of automated processes, whole industries have migrated toward the incorporation of computers into their products. Today we see computer systems in telecommunication devices, televisions, home appliances, automobiles, industrial process controllers, musical instruments, games, and vending machines, not to mention aircraft, spacecraft, weapons systems, and data network servers. It could be said now that it is the demand for faster, more precise, more application-specific, more robust computer systems that is driving the computer industry toward further advances instead of advances in the industry identifying opportunities for application of computer devices. We are experiencing an era where demands are pulling enabling technologies along.
Today, there are literally thousands of different devices that can be connected to a computer bus. And today's data buses are no longer 8 bits wide; 64-bit buses are more commonly found with new devices coming to the field having buses with widths of 128 bits or more. In addition, today's systems no longer consist of only one device that is capable of initiating a transaction over the data bus. A high-end performance computer may have a CPU that is dedicated to performing general purpose computations, a graphics processor that performs video-intensive computations, and a digital signal processor (DSP) that performs intensive audio signal manipulations. The high-end system may also have a communications processor that is dedicated to interacting with other computers over a network. And all of these processors must communicate over a bus to memory, to I/O logic, and to innumerable other kinds of special-purpose devices. In fact, it is not uncommon today to find four or more CPUs in a system configuration, each of which is capable of initiating bus transactions. Moreover, all of these elements of the computer system, to include the system bus itself, may be fabricated as part of a single integrated circuit device.
As devices have become more diverse, more complex, and more capable, the rules for communication between devices has also evolved. Bus protocols today account for the fact that multiple devices can initiate data transfers. In fact, many present day CPUs have on-chip bus arbitration logic that enables them to interact over a shared data bus with other like CPUs. The arbitration logic grants bus access to requesting devices according to some predefined algorithm so that all devices on the bus can effect their required data transactions in a timely manner. When a device requests access to the bus, the arbitration logic may either grant or refuse access, so that contention between devices is avoided. Typically following a grant, the requesting device conducts its transaction and then relinquishes the bus so that other devices can conduct transactions. So devices must request access to the bus, they must wait for access to be granted by the arbitration logic, then they are allowed to conduct their data transaction over the bus.
Request, grant, transfer. Request, grant, transfer. One can observe that two-thirds of the bus protocol steps are devoted to performing overhead functions, that is, functions that do not transfer data. And system designers recognize that tying up a shared medium to perform functions outside of the primary intent of the medium is disadvantageous to all the devices that share the medium. This observation has resulted in the development of a technique in the art to drastically improve the efficiency of data transactions over a bus commonly referred to as a burst transaction.
A burst transaction is distinguished from a single transaction in that, rather than transferring data over the bus for one clock e following reception of a grant, a device capable of a burst transaction is allowed to transfer data for multiple clock cycles before it must relinquish the bus. For example, the Pentium II® bus is a 64-bit data bus that allows 32-bytes of data to be transferred in a burst transaction consisting of four back-to-back cycles, each cycle transferring eight bytes of data. Hence, rather than exhibiting request, grant, transfer, a device capable of bursting over the Pentium II® system bus exhibits request, grant, transfer, transfer, transfer, transfer-a two-fold increase in bus ef
Huffman James W.
Huffman Richard K.
MIPS Technologies Inc.
Shin Christopher B.
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