Burst clock memory circuit

Details Burst clock memory circuit Burst clock memory circuit

1998-01-27

2000-07-11

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

713400, G06F 1200

Patent

active

060887761

ABSTRACT:
A memory circuit for processing a data signal, supplied together with a write clock signal from a counterpart station, into a processed signal. The data signal is stored in a first memory in response to the write clock signal. A first clock producing circuit produces a first clock signal which is synchronous with the write clock signal and has a transmission rate obtained by averaging that of the write clock signal. The first clock signal is of a burst clock form and supplied to the first memory to make the first memory output the data signal therefrom. A local processing circuit is responsive to the first clock signal and processes the data signal, outputted from the first memory, into the processed signal which is supplied to a signal processing circuit.

REFERENCES:
patent: 5034962 (1991-07-01), Yamamoto et al.
patent: 5475440 (1995-12-01), Kobayashi et al.
patent: 5502752 (1996-03-01), Averbuch et al.
patent: 5642487 (1997-06-01), Flynn et al.
patent: 5815689 (1998-09-01), Shaw et al.
patent: 5946712 (1999-08-01), Lu et al.

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