Burst address generator having two modes of operation employing

Details Burst address generator having two modes of operation employing Burst address generator having two modes of operation employing

1995-12-21

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711219, 365240, G06F 1328

Patent

active

058359702

ABSTRACT:
An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2.sup.N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2.sup.N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

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