Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-07-17
2001-09-04
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S222000
Reexamination Certificate
active
06285610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a burn-in test circuit, and more particularly, to a burn-in test circuit for a semiconductor memory device which is capable of burn-in testing at a wafer and package level at a low expense with a high efficiency by controlling a level of an external power supply voltage to drive word lines.
2. Description of the Background Art
Burn-in testing is a kind of test to remove any inferiority of a semiconductor memory device in advance that may cause various deficiencies in actual use of the semiconductor memory device. Generally, the testing is performed in a different accelerated condition (i.e., a voltage and a temperature is more highly set) to an actual use of it in order to promote an efficiency of the testing).
FIG. 1
is a schematic block diagram of a semiconductor memory device using a burn-test circuit in accordance with a conventional art.
As shown in the drawing, the burn-in test circuit includes a command decoder
10
for generating a burn-in control signal BEN according to a burn-in command COM generated by an external control circuit (not shown); an auto refresh address counter
20
for generating an internal address signal IADD according to an auto-refresh command AREF; an address multiplexer
30
for multiplexing the internal address signal IADD and an external address signal EADD under the control of the auto-refresh command AREF and generating an address signal ADD used for driving word lines; a row decoder
40
for generating a word line drive signal WLEN upon receipt of the burn-in control signal BEN and the address signal ADD; and a memory cell array
50
having a plurality of memory cells driven by the word line drive signal WLEN.
FIG. 2
is a detailed circuit diagram of a row decoder
40
of the semiconductor memory device using the burn-in test circuit in the conventional art.
A general row decoder has a combination of a plurality of logic gates which receives plural number (N) of address signals ADD
0
~ADD(n−1) and outputs plural number (2N) of decoding signals AX
0
~AX(N−1).
FIG. 2
shows a circuit diagram of a row decoder
40
in which two address signals ADD
0
and ADD
1
are decoded.
As shown in the drawing, the row decoder
40
includes a pre-decoder
41
having a first and a second AND gates AND
1
and AND
2
for ANDing a first and a second address signals ADD
0
and ADD
1
and outputting a first and a second signals AX
0
and AX
1
, a first and a second inverters INV
1
and INV
2
for respectively inverting the first and the second address signals ADD
0
and ADD
1
, and a third and a fourth AND gates AND
3
and AND
4
for ANDing the output signals from the first and the second inverters INV
1
and INV
2
and outputting a third and a fourth address signals AX
2
and AX
3
; and a word line drive unit
42
having a first PMOS transistor PM
1
connected in series to a booster voltage VPP and a ground voltage VSS, a gate of which receives a control signal WPRE, a first to a fourth NMOS transistors NM
1
~NM
4
, each gate of which receives a first to a third address signals AX
0
~AX
3
, respectively, a third inverter INV
3
for inverting a voltage of a drain commonly connected to the first PMOS transistor PM
1
and the first NMOS transistor NM
1
so as to drive word lines, and a fifth NMOS transistor NM
5
, a drain of which is commonly connected to the first PMOS transistor PM
1
and the first NMOS transistor NM
1
, a source thereof is connected to the ground voltage VSS, and a gate thereof receives a burn-in enable signal BEN, to thereby simultaneously drive all word lines.
The operation of the semiconductor memory device using the burn-in test circuit in accordance with the conventional art constructed as described above will now be explained with reference to the accompanying drawings.
First, in a burn-in test mode, an accelerated condition suitable for burn-in testing is set at a high voltage and at a high temperature. And, a pre-set burn-in command COM is inputted to generate a burn-in enable signal BEN at the command decoder
10
. And then, the semiconductor memory device is set in a state suitable for burn-in testing by using the burn-in enable signal BEN.
In detail, after the semiconductor memory device is set on an accelerated condition suitable for burn-in testing, as shown in
FIG. 3A
, a pre-set burn-in command COM is applied from an external control circuit (not shown). Then, as shown in
FIG. 3B
, a burn-in enable signal BEN is accordingly generated from the command decoder
10
.
In this respect, when the burn-in enable signal BEN becomes high level, the NMOS transistor NM
5
of the row decoder
40
is turned on, according to which all word lines become high level VPP regardless of the internal address signal IADD and the external address signal EADD, and thus, the memory cell is in a suitable state for burn-in testing.
Then, a stress voltage is applied to all word lines by a word line stress input unit (not shown) to perform burn-in testing.
Meanwhile, in a refresh mode, the auto-refresh address counter
20
sequentially increases the internal address signal IADD at every positive edge of the auto-refresh command AREF, that is, a clock signal, so that the memory cells can be sequentially refreshed.
The multiplexer
30
multiplexes the internal address signal IADD or the external address signal EADD under the control of the auto-refresh command AREF and outputs it to the row decoder
40
. In case of an auto-refresh mode, the multiplexer
30
selectively inputs the internal address signal IADD to the row decoder
40
.
Accordingly, the row decoder
40
decodes the internal address signal IADD to drive selected word lines and performs sequential refreshing operation.
Meanwhile, in a normal operation mode, the multiplexer
30
outputs the external address signal EADD to the row decoder
40
, so that the word lines of the memory cell array
40
are driven.
However, referring to the burn-in circuit of the conventional art, since the burn-in command COM is to be inputted from an external source for burn-in testing, an external device is required for generating the burn-in command COM, causing an extra expense for constructing the additional external circuit, and also, since the external burn-in command COM is inputted regardless of the internal state, an efficiency in the burn-in testing is degraded.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a burn-in test circuit in which word lines are driven by controlling a level of an external power supply voltage, rather than by a control signal from an external source, so that burn-in testing is performed at a wafer and package level at a low expense with high efficiency.
To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described herein, there is provided a burn-in test circuit for semiconductor memory device consisting of a memory cell array having a plurality of memory cells and a row decoder for outputting a word line drive signal so as to drive word lines of the memory cell array, including a reference voltage generating unit for generating a reference voltage; a voltage sensing unit for sensing a power supply voltage level; a self-refresh timer for outputting a clock signal; a burn-in control unit for outputting a burn-in enable signal according to the output signal from the voltage sensing unit and the output signal from the self-refresh timer; an auto-refresh address counter for generating an internal address signal according to the burn-in enable signal of the burn-in control unit and the auto-refresh command; and a multiplexer for multiplexing the external address signal and the internal address signal under the control of the auto-refresh command and the burn-in control signal.
REFERENCES:
patent: 5452253 (1995-09-01), Choi
patent: 6108252 (2000-08-01), Park
Hoang Huan
Hyundai Electronics Industries Co,. Ltd.
Yoha Connie C.
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