Burn-in stress circuit for semiconductor memory device

Details Burn-in stress circuit for semiconductor memory device Burn-in stress circuit for semiconductor memory device

1997-05-19

1999-09-07

Mai, Son

Static information storage and retrieval

Read/write circuit

Testing

36523006, G11C 700

Patent

active

059497246

ABSTRACT:
A burn-in stress circuit for a semiconductor memory device. A burn-in enable signal generator generates a burn-in enable signal in response to a plurality of control signals. A wordline predecoder generates a wordline driving voltage for driving a wordline in response to the burn-in enable signal and another a plurality of control signals. A wordline decoder applies the wordline driving voltage to the wordline in response to the burn-in enable signal and another plurality of control signals. To reduce the stress testing time by stressing multiple rows of a memory array simultaneously, all of the wordlines (rows) are stressed and or tested at the same time. To select all of the wordlines, the wordlines are selected sequentially, but each selected wordline is held in a selected state by a latching mechanism while all of the other wordlines are being selected as well. When all of the wordlines (or a desired subset) have been selected, the burn-in stress test begins.

REFERENCES:
patent: 4868823 (1989-09-01), White
patent: 5258954 (1993-11-01), Furuyama
patent: 5265100 (1993-11-01), McClure
patent: 5276647 (1994-01-01), Matsui
patent: 5301155 (1994-04-01), Wada
patent: 5615164 (1997-03-01), Kirihata

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