Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-07-13
2003-04-08
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06546510
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuits, and more particularly to circuits for detecting operational modes while a semiconductor integrated circuit is undergoing a burn-in operation.
BACKGROUND OF THE INVENTION
An important step in ensuring the reliability of semiconductor devices is “burn-in.” While modern semiconductor manufacturing processes result in very low defect densities, defects can still occur due to uncontrollable factors, such as inherent variations in the manufacturing process. While some types of defects may be immediately detected by testing the devices, other types of defects can result in “infant” mortality. Infant mortality defects, while not immediately apparent, arise after a device has been operational for a short period of time, resulting in semiconductor devices which have an abnormally short lives.
In order to eliminate infant mortality defects, semiconductor devices are often screened in a “back-end” (i.e., post wafer fabrication) manufacturing step, referred to as “burn-in.” During burn-in, power is applied to semiconductor devices for a prolonged period of time to induce infant mortality failures. To accelerate infant mortality failures, the burn-in step can be conducted at elevated power supply voltages and/or temperatures. In the latter case, semiconductor devices are powered-up within a burn-in oven. In the former case, the semiconductor devices may include specialized circuitry to apply a higher than normal voltage to the circuits within.
In some burn-in operations, the functions of a semiconductor device are exercised under the burn-in stress. In such cases, the semiconductor is essentially “tested” during burn-in. For semiconductor devices having relatively few functions, the testing process can be rapidly performed. For more complex semiconductor devices, the testing process can be relatively lengthy. For example, in the case of semiconductor memory devices, it may be desirable to test each memory location during burn-in in order to screen all the memory cells of the device for infant mortality type defects. Such an approach can require relatively long periods of time, as millions of such memory cells have to be accessed by unique addresses.
One way in which to increase the speed at which a semiconductor device's functions may be exercised, is to include built-in testing circuits on the semiconductor device itself. Such testing circuits are often referred to as “design-for-test” (DFT) circuits. Among the types of DFT circuits in semiconductor memory devices, are those which automatically cycle through the various memory locations of the memory device, reading and writing data into each memory location. In larger semiconductor devices, which are internally divided into banks, the DFT circuit may exercise the various semiconductor memory device functions on a bank-by-bank basis, or on a multiple bank basis (i.e., write data into all banks simultaneously).
The DFT circuits are usually implemented by placing the semiconductor device in a DFT mode. For example, in the case of a large density semiconductor memory device, during burn-in, the DFT circuits would initially access a first bank of memory cells, and then access a second bank, and continue in this manner until the functions of each bank of the device have been exercised.
A problem associated with burn-in can arise when a command is applied to the semiconductor device to place it in a burn-in mode, and the device, due to noise or other reasons does not actually enter the burn-in mode. In such an event, the device may not receive the increased burn-in voltage, and hence infant mortality defects can be missed. Similar problems can arise in the event the semiconductor device does not enter the correct DFT mode during burn-in, or does not correctly transition from one DFT mode (activating a first bank, for example) to a another (activating a second bank, for example). In such an event, a certain portion of the semiconductor device may not be stressed by the burn-in operation and can subsequently fail at a later time.
It would be desirable to arrive at some way to ensure that devices are properly placed in a burn-in mode, and that DFT circuits within devices are properly enabled during a burn-in operation.
SUMMARY OF THE INVENTION
According to the preferred embodiment, a synchronous dynamic random access memory (SDRAM) includes a burn-in mode, in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, instead of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM is properly exercised during burn-in.
According to one aspect of the preferred embodiment, the SDRAM includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs. In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs.
According to another aspect of the preferred embodiment, the SDRAM includes a number of memory cell banks that must be activated in order to access the memory cells within. Activation of a memory cell bank while the SDRAM is in the burn-in monitor mode will automatically take the SDRAM out of the burn-in monitor mode. This eliminates the need for a separate “exit burn-in monitor test” command each time the memory cells are to be accessed.
According to another aspect of the preferred embodiment, the SDRAM includes a clock buffer circuit that provides an internal clock signal for the SDRAM. The clock buffer circuit automatically introduces hysteresis into the internal clock signal in a burn-in mode. The test can query the device to verify that the correct DFT parallel test, mode register settings such as burst length and read latency, clock hysteresis activation, and burn-in stress voltage are being applied.
REFERENCES:
patent: 5463636 (1995-10-01), Nakayama
patent: 5557559 (1996-09-01), Rhodes
patent: 5956279 (1999-09-01), Mo et al.
patent: 6037792 (2000-03-01), McClure
Hii Francis
Mazumder Kallol
Smith Scott E.
Brady III W. James
Chase Shelly A
De'cady Albert
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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