Burn-in checking apparatus for semiconductor memory device

Details Burn-in checking apparatus for semiconductor memory device Burn-in checking apparatus for semiconductor memory device

1997-08-05

1998-09-01

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36523006, 36523008, G11C 700

Patent

active

058020012

ABSTRACT:
An improved burn-in checking apparatus for a semiconductor memory device in which a latch-type decoder is connected between a row address predecoder for decoding an internal or external address when it is inputted and a word line driving unit for driving a word line unit to latch a high level signal for keeping an enabled condition, so that when a burn-in flag is applied, an output from the row address predecoder is decoded again, and a word line selected according to such decoding is continuously enabled even when a next word line is selected in accordance with decoding of a next row address signal. The apparatus has the advantage that by sequentially enabling all the word lines within almost one minute and latching the enabled condition until the completion of the burn-in checking, the actual time consumed in real checking is little increased, and in addition, the contamination of the device characteristic due to an increase in a momentary current amount can be effectively prevented.

REFERENCES:
patent: 5640353 (1997-06-01), Ju
patent: 5654930 (1997-08-01), Yoo et al.

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