Active solid-state devices (e.g. – transistors – solid-state diode – Avalanche diode – With means to limit area of breakdown
Reexamination Certificate
2002-06-27
2003-08-12
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Avalanche diode
With means to limit area of breakdown
C257S199000, C257S551000, C257S603000, C257S604000
Reexamination Certificate
active
06605859
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to Zener diodes, and more particularly, to a buried Zener diode structure and method of manufacture that requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation.
2. Description of the Prior Art
Conventional “surface” Zener reference diodes exhibit long-term drift due to impurities and other oxide charges that can build up over time. This phenomenon is known as “Zener walkout”. Buried Zener diodes do not suffer these problems, since such diodes possess stable long-term performance. Buried Zener diodes generally require additional process steps beyond those typically used in a “Standard” bipolar flow. In view of the foregoing, it would be both advantageous and desirable to provide a buried Zener diode structure and method of manufacture that does not require additional process steps beyond those typically used in a “Standard” bipolar flow. Some buried Zener diode structures representative of the present state of the art are described in the U.S. patents discussed herein below.
U.S. Pat. No. 4,833,509, entitled Integrated Circuit Reference Diode And Fabrication Method Therefor, issued May 23, 1989, to Hickox et al., discloses an N+ buried layer, but that must be oversized to compensate for alignment after the EPI is grown. This structure also requires two N+ diffusions, thus requiring extra mask steps.
U.S. Pat. No. 5,027,165, entitled Buried Zener Diode, issued Jun. 25, 1991, to Doluca, discloses a buried Zener diode structure, but that undesirably requires an additional P+ diffusion.
U.S. Pat. No. 4,136,349, entitled IC Chip With Buried Zener Diode, issued Jan. 23, 1979, to Tsang, discloses a structure that requires both an oversized N+ layer as well as an extra P+ diffusion.
U.S. Pat. No. 4,683,483, entitled Subsurface Zener Diode And Method Of Making, issued Jul. 28, 1987, to Burnham et al., discloses a structure that requires the N+ layer to be oversized, requires and extra mask step, requires an emitter etch to clear the isolation oxide, and has additional alignment issues to deal with.
U.S. Pat. No. 4,742,021, entitled Subsurface Zener Diode And Method Of Making, issued May 3, 1988, to Burnham et al., discloses a structure that requires the N+ layer to be oversized, requires a Pwell diffusion, and also requires an additional step comprising etching the emitter mask through the isolation oxide.
U.S. Pat. No. 4,177,095, entitled Process For Fabricating An Integrated Circuit Subsurface Zener Diode Utilizing Conventional Processing Steps, issued Dec. 4, 1979, to Nelson, discloses a structure that requires an emitter diffusion through an isolation oxide (extra mask step), the N+ layer to be oversized, and a breakdown that is set by ISO/Emitter doping, that is generally not well controlled.
U.S. Pat. No. 4,127,859, entitled Integrated Circuit Subsurface Zener Diode, issued Nov. 28, 1978, to Nelson, discloses a structure that requires the N+ layer to be oversized.
U.S. Pat. No. 5,179,030, entitled Method Of Fabricating A Buried Zener Diode Simultaneously With Other Semiconductor Devices, issued Jan. 12, 1993, to Hemmah, discloses a structure in which the substrate is the anode and that does not have a buried junction.
SUMMARY OF THE INVENTION
The present invention is directed to a buried Zener diode structure and method of manufacture that requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation.
In one aspect of the invention, a buried Zener diode is provided where the N++/P+ junction is removed from the silicon surface without requiring additional process steps beyond those typically used in a “Standard” bipolar flow.
In another aspect of the invention, a buried Zener diode is provided having more stable long-term performance than conventional “surface” Zener reference diodes without requiring additional process steps beyond those typically used in a “Standard” bipolar flow.
In yet another aspect of the invention, a buried Zener diode is provided having a P-type buried isolation (PBL) to make contact to the anode of the Zener diode.
REFERENCES:
patent: 4127859 (1978-11-01), Nelson
patent: 4136349 (1979-01-01), Tsang
patent: 4177095 (1979-12-01), Nelson
patent: 4601760 (1986-07-01), Hemmah et al.
patent: 4646114 (1987-02-01), Vinn et al.
patent: 4651178 (1987-03-01), Avery
patent: 4652895 (1987-03-01), Roskos
patent: 4683483 (1987-07-01), Burnham et al.
patent: 4742021 (1988-05-01), Burnham et al.
patent: 4833509 (1989-05-01), Hickox et al.
patent: 5027165 (1991-06-01), Doluca
patent: 5179030 (1993-01-01), Hemmah
patent: 5241213 (1993-08-01), Hull
patent: 5869882 (1999-02-01), Chen et al.
Oglesby, Jr. Darrel C.
Romas, Jr. Gregory G.
Brady III W. James
Elms Richard
Garner Jacqueline J.
Menz Douglas
Telecky , Jr. Frederick J.
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