Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-05
2002-07-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000, C257S513000
Reexamination Certificate
active
06414361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a shallow trench isolation structure and a method for forming the same to isolate active regions within a semiconductor device and, more particularly, to a burled shallow trench isolation structure and a method for forming the same to prevent latch-up in a complementary metal-oxide semiconductor (“CMOS”) integrated circuit.
2. Description of the Related Art
A CMOS integrated circuit device, by definition, includes at least one n-type metal-oxide semiconductor (“NMOS”) formed in a p-well region and one p-type metal-oxide semiconductor (“PMOS”) formed in an n-well region of the device.
FIG. 1
shows a conventional CMOS device. Referring to
FIG. 1
, an NMOS includes source and drain regions, a channel region therebetween, an n-type gate NGate separated from the channel region by a gate oxide, and oxide or nitride spacers on the sides of n-type gate NGate. Each of the drain and source regions includes a lightly-doped region n
−
and a heavily-doped region n
+
. Similarly, a PMOS includes source and drain regions, a channel region therebetween, a p-type gate PGate separated from the channel region by a gate oxide, and oxide or nitride spacers on the sides of p-type gate PGate. Each of the drain and source regions includes a lightly-doped region p
−
and a heavily-doped region p
+
.
The formation of the n-type and p-type MOS field-effect transistors (“MOSFETs”) leads to the formation of parasitic bipolar junction transistors (“BJTs”). During normal device operations, parasitic transistors are not turned-on and therefore do not affect device operations. However, under certain transient conditions, such as voltage surges, parasitic BJTs may be turned-on and the device is said to be “latched-up.”
A parasitic BJT may be turned-on by migrating charge carriers, such as holes migrating to the base, or the n-well region, of a pnp BJT, and electrons migrating to the base, or the p-well region, of an npn BJT. Charge carriers can also migrate from the substrate beneath the active regions of the CMOS circuit. In addition, because the collector of a pnp BJT is connected to the base of an npn BJT and the collector of the npn BJT is connected to the base of the pnp BJT, when one parasitic BJT is turned-on by the migrating charge carriers, the other BJT will also be turned on. Further, if one npn-pnp BJT pair is turned-on, other parasitic BJT pairs in the device will likewise be turned-on, thereby creating a feedback loop within the device. Such a feedback loop consumes power, reduces device speed, and sometimes renders the device inoperative. Once formed, the feedback loop cannot be severed easily. The probability of latch-up increases as device size becomes smaller because undesired charge carriers that create the latch-up triggering current have a greater chance of reaching the areas of the device to trigger latch-up.
Latch-ups may be prevented by stopping the migration of charge carriers or substantially reducing the number of migrating charge carriers. Two known methods have been employed to prevent latch-ups. One method places insulating materials in the shallow surface between active regions of the device to act as barriers to carrier charge flow. These insulating barriers are known as shallow trench isolation (“STI”) structures. The other known method employs “guard rings,” or heavily doped materials, that act as “sinks” to divert the undesired charge carriers away from the parasitic BJTs. Guard rings are inserted from the surface to form vertical barriers to charge carrier flow.
Because the depth of the STIs and guard rings is limited by the fabrication process, charge carriers, may still migrate underneath them and therefore neither method, by itself or in combination, effectively prevents the flow of carriers to or from the substrate. This charge carrier flow is also known as leakage current. As shown in
FIG. 1
, although the flow of carriers between the p- and n-wells is prevented by the combination of STIs and guard rings, leakage current flows through the substrate between the n-well and p-well regions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a buried shallow trench isolation structure and a method for forming the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a substrate and a layer of single-crystal semiconductor material disposed over the substrate. The integrated circuit device also includes a first isolation structure of dielectric material formed within the substrate. The first isolation structure is in contact with the layer and its thickness is less than that of the substrate. The integrated circuit device additionally includes a second isolation structure of dielectric material formed within the layer and extends over the first isolation structure to reduce leakage current in the substrate.
In another aspect, the first isolation structure of the invention is in contact with the second isolation structure.
In yet another aspect, the invention may be defined by:
D
-
G
E
≲
0.3
where D is the thickness of the layer, G is the thickness of the second isolation structure and E is the width of the second isolation structure.
Also in accordance with the invention, there is provided an integrated semiconductor device that includes a semiconductor substrate having a first thickness and a layer of single-crystal semiconductor material disposed over the substrate that includes at least one n-well region and at least one p-well region adjacent the n-well region. The integrated semiconductor device also includes a first isolation structure formed within the substrate and in contact with the layer wherein the first isolation structure is dielectric and has a thickness less than the first thickness, and a second isolation structure formed within the layer and disposed between the n-well region and the p-well region wherein the second isolation structure is dielectric. In addition, the second isolation structure extends over the first isolation structure to substantially reduce leakage current in the substrate to prevent device latch-up and to isolate the n-well region from the p-well region.
Further in accordance with the invention, there is provided a method for forming a buried shallow trench isolation structure that includes the steps of defining a substrate, forming at least one trench on the substrate, providing a dielectric material in the trench to form a first isolation structure, growing an epitaxial layer over the substrate and the first isolation structure, forming at least one trench in the epitaxial layer wherein the trench of the epitaxial layer extends over the first isolation structure, and providing a dielectric material in the trench of the epitaxial layer to form a second isolation structure.
In one aspect of the invention, the step of providing a dielectric material to form a first isolation structure includes a step of oxidation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4902639 (1990-02-01), Ford
patent: 5326991 (1994-07-01), Takasu
patent: 5675176 (1997-10-01), Ushiku et al.
patent: 5677564 (1997-10-01), McCormack et al.
patent: 5712185 (1998-01-01), Ts
Lin Shi-Tron
Wong Shyh-Chyi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Loke Steven
Winbond Electronics Corporation
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