Buried PIP capacitor for mixed-mode process

Details Buried PIP capacitor for mixed-mode process Buried PIP capacitor for mixed-mode process

2002-10-09

2003-12-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06664580

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a buried Polysilicon Insulator Polysilicon (PIP) capacitor for mixed-mode semiconductor device processing.
(2) Description of the Prior Art
With the increased complexity of semiconductor devices has come an increased demand for concurrent creation of active semiconductor devices such as Field Effect Transistors (FET) and capacitors that are in relatively close proximity to the active semiconductor devices. This mixing of active and passive devices is referred to as mixed-mode fabrication of semiconductor components.
The conventional method that is used to simultaneously create a FET and a capacitor is highlighted using FIG.
1
. In
FIG. 1
is shown a cross section of a semiconductor substrate
10
. Defined in the surface of the substrate
10
have been a p-well
12
and a n-well
14
.
A capacitor
11
is created overlying the p-well
12
, a PMOS gate electrode
13
is created overlying the n-well
14
. The p-well
12
is electrically insulated from the n-well
14
by the Shallow Trench Isolation (STI) region
18
that has been created in the surface of substrate
10
. STI region
16
is the field isolation region over which the dual layer polysilicon capacitor is being created while STI region
20
further defines and insulates the n-well
14
.
After the regions of insulation (
12
,
14
,
16
,
18
and
20
) have been defined in the surface of the substrate
10
, a thin layer
26
of oxide of created over the surface of the substrate
10
. A layer of polysilicon is then deposited, patterned and etched, using conventional methods of photolithography and patterning, simultaneously creating the gate electrode
28
and the first layer
29
of polysilicon of the capacitor
11
.
The active regions
22
and
24
, which form the source and drain regions of the gate electrode
13
, are next created by impurity implantation into the surface of the substrate
10
that is self aligned with the structure
26
/
28
of gate electrode
13
. Low resistivity contacts to the active regions in the surface of the substrate and to the gate electrode are next established using convention methods of salicidation.
Salicidation is performed by depositing a layer of metal comprising refractory metal, such as tungsten, titanium, tantalum, molybdenum and platinum, over the surface of the structure and by then heat treating the structure in order to cause the deposited metal to interact with the underlying silicon. In this manner are formed silicide surface regions overlying the source and drain regions
22
and
24
(the silicided surfaces are not highlighted in FIG.
1
), the contact
30
with the gate electrode and the layer
32
overlying the layer of first polysilicon
29
. The layers
26
,
28
and
30
form the gate electrode, the layers
29
and
32
form the first electrode of capacitor
11
. At this time, the gate electrode is typically completed with the creation of gate spacers on the sidewalls of the column
26
,
28
and
30
.
The common practice of first creating Lightly doped Diffusion (LDD) regions in the surface of the substrate
10
, self aligned with the gate electrode and immediately after the gate electrode has been formed, is well known in the art. For these applications, the deep source/drain implant is performed after the gate spacers have been formed on sidewalls of the gate structure and in addition to the LDD implants.
For the completion of the formation of the capacitor
11
, a patterned layer
34
of capacitor dielectric is created overlying the lower electrode
29
/
32
of capacitor
11
after which a patterned second layer
36
of polysilicon is created that forms the second electrode of capacitor
11
.
Capacitor
11
therefore comprises two layers of polysilicon, separated by a layer of insulation (capacitor dielectric), from which the name polysilicon-insulator-polysilicon (PIP) is derived. After this, the components of the structure must be made accessible for external connection, which is done by depositing a layer
38
of dielectric over the structure, creating openings in this layer
38
of dielectric and filling these openings with a conductive material, typically metal.
In this manner are created metal plug
40
, which connects to the second electrode of capacitor
11
, metal plug
42
which connects to the source region of gate electrode
13
, metal plug
44
which connects to the gate electrode
13
and metal plug
46
which connects to the drain region of gate electrode
13
.
The process can be summarized as follows:
gate oxide growth
poly 1 deposition
capacitor dielectric film deposition
poly 2 deposition
poly 2 patterning
poly 1 patterning
NLDD/PLDD implants
spacer formation
N′/P′ implants for source/drain regions, and
salicide formation.
The above highlighted mixed-mode process of creating a PIP capacitor while simultaneously creating a gate electrode has a number of disadvantages. The process results in high topography and makes the subsequent back-end-of-line (BEOL) processing more difficult. In addition, an extra thermal cycle is required in order to anneal the PIP insulator film to maintain desired quality levels. These latter requirements have a detrimental effect on a standard logical device. These disadvantages make a mixed-mode process more complex than the standard logic process.
U.S. Pat No. 6,165,861 (Liu et al.), U.S. Pat. No. 6,103,622 (Huang), U.S. Pat. No. 4,419,812 (Topich), U.S. Pat. No. 5,913,126 (Oh et al.) show related capacitor processes and structures.
SUMMARY OF THE INVENTION
A principle objective of the invention is to enable mixed-mode processes for the creation of a PIP capacitor and a gate electrode such that this process does not influence gate electrode topography.
Another objective of the invention is to provide a method of creating in mixed-mode a PIP capacitor and gate electrodes such that processing steps that are required for the creation of the PIP capacitor have no influence on standard logic devices.
In accordance with the objectives of the invention a new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created over the surface of the, substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted into the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon. The mixed-mode process is then resumed with conventional processing of creating a layer of gate oxide, the deposition and patterning of a second layer of polysilicon and the additional Back-End-Of-Line (BEOL) processing that is required to complete the mixed-mode structure of a PIP capacitor and a gate electrode.


REFERENCES:
patent: 4419812 (1983-12-01), Topich
patent: 5913126 (1999-06-01), Oh et al.
patent: 6103622 (2000-08-01), Huang
patent: 6165861 (2000-12-01), Liu et al.
patent: 6306720 (2001-10-01), Ding
patent: 6373083 (2002-04-01), Oh
patent: 6468855 (2002-10-01), Leung et al.

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