Buried magnetic tunnel-junction memory cell and methods

Details Buried magnetic tunnel-junction memory cell and methods Buried magnetic tunnel-junction memory cell and methods

2003-03-05

2004-11-16

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S003000, C438S631000, C438S637000, C438S669000, C438S680000, C438S700000, C438S753000

Reexamination Certificate

active

06818549

ABSTRACT:

TECHNICAL FIELD
This invention relates to magnetic tunnel-junction devices and more particularly to information storage devices such as magnetic random access memory (“MRAM”) devices incorporating buried magnetic tunnel-junction devices, and to methods for making and using such devices.
BACKGROUND
A typical MRAM device includes an array of memory cells, word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line. In one type of MRAM device, each memory cell includes a tunnel junction such as a spin-dependent tunneling (“SDT”) junction. The magnetization of an SDT junction assumes one of two stable orientations at any given time. These two stable magnetic orientations, parallel and anti-parallel, represent logic values of “0” and “1.” The magnetization orientation, in turn, affects the resistance of the SDT junction. Resistance of the SDT junction has a first value (R
p
) if the magnetization orientation is parallel and has a higher second value (R
a
) if the magnetization orientation is anti-parallel. The magnetization orientation of a SDT junction and, therefore, its logic state may be read by sensing its resistance state. MRAM integrated circuits using magnetic tunnel junctions can provide nonvolatile information storage especially useful in extending the applications of CMOS integrated circuit technology.
Defective SDT junctions can be created during manufacture by various mechanisms, such as electrostatic discharges, handling errors, and circuit anomalies such as voltage spikes. Each defective SDT junction can cause a bit error. In a crosspoint MRAM array that does not use transistor switches or diodes to isolate memory cells from one another, a short-circuited SDT junction can also render other memory cells in the same column and row unusable. Thus, a single shorted SDT junction can cause column-wide and row-wide errors as well. When data is read back from the MRAM device, error correcting codes (ECC) may be used to recover data from complete rows and columns of unusable SDT junctions. However, ECC for a thousand or more bits in a single column or row is costly, both from a time standpoint and a computational standpoint. Moreover, an MRAM device is likely to have more than one shorted SDT junction. If an MRAM device contains many unusable SDT junctions, that device is rejected at the manufacture stage. Thus, electrostatic discharge, handling errors, and circuit anomalies can reduce manufacturing yield. Prevention of damage from these mechanisms is expensive and difficult to implement.
The use of transistor switches or isolating diodes to isolate memory cells from one another is known in the art, but such devices increase complexity and are typically larger than the minimum attainable geometry and thus limit the size of memory cell arrays.
Improved isolation of magnetic tunnel-junction memory cells is needed, and magnetic tunnel-junction memory cells that can be manufactured by relatively simple processes with diminished incidence of junction defects are especially desirable.


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