Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-12-04
2007-12-04
Smith, Matthew (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S373000, C257S375000, C257S376000, C257S409000
Reexamination Certificate
active
10951283
ABSTRACT:
Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
REFERENCES:
patent: 4161417 (1979-07-01), Yim et al.
patent: 4980747 (1990-12-01), Hutter et al.
patent: 5138420 (1992-08-01), Komori et al.
patent: 5220192 (1993-06-01), Owens et al.
patent: 5376816 (1994-12-01), Nishigoori et al.
patent: 5386136 (1995-01-01), Williams et al.
patent: H1435 (1995-05-01), Cherne et al.
patent: 5501993 (1996-03-01), Borland
patent: 5641982 (1997-06-01), Takahashi
patent: 5719733 (1998-02-01), Wei et al.
patent: 5728612 (1998-03-01), Wei et al.
patent: 5821572 (1998-10-01), Walker et al.
patent: 5835986 (1998-11-01), Wei et al.
patent: 5843813 (1998-12-01), Wei et al.
patent: 5858828 (1999-01-01), Seliskar et al.
patent: 5880515 (1999-03-01), Bartlett
patent: 5894153 (1999-04-01), Walker et al.
patent: 5904551 (1999-05-01), Aronowitz et al.
patent: 5963801 (1999-10-01), Aronowitz et al.
patent: 5966599 (1999-10-01), Walker et al.
patent: 5985705 (1999-11-01), Seliskar
patent: 6063672 (2000-05-01), Miller et al.
patent: 6069048 (2000-05-01), Daniel
patent: 6136672 (2000-10-01), Bourdelle et al.
patent: 6144076 (2000-11-01), Puchner et al.
patent: 6171967 (2001-01-01), Jun
patent: 6309940 (2001-10-01), Lee
patent: 6316817 (2001-11-01), Seliskar et al.
patent: 6319793 (2001-11-01), Bartlett et al.
patent: 6333520 (2001-12-01), Inoue
patent: 6395611 (2002-05-01), Belk et al.
patent: 6462378 (2002-10-01), Kim
patent: 6472715 (2002-10-01), Liu et al.
patent: 6476451 (2002-11-01), Wong
patent: 6492270 (2002-12-01), Lou
patent: 6501155 (2002-12-01), Okawa
patent: 6514824 (2003-02-01), Randazzo et al.
patent: 6525377 (2003-02-01), Seliskar
patent: 6673635 (2004-01-01), Hellig et al.
patent: 6706583 (2004-03-01), Comard
patent: 6787858 (2004-09-01), Zitouni et al.
patent: 6847065 (2005-01-01), Lum
patent: 6864152 (2005-03-01), Mirbedini et al.
patent: 6885078 (2005-04-01), Bartlett et al.
patent: 6940170 (2005-09-01), Parikh
patent: 2002/0182884 (2002-12-01), Bernkopf et al.
patent: 2003/0077875 (2003-04-01), Mandelman et al.
patent: 2004/0075144 (2004-04-01), Zitouni et al.
Silicon Processing for the VLSI Era, vol. 1: Process Technology, By S. Wolf and R.N. Tauber Published by Lattice Press in 2000. p. 256-259; 406 and 407.
Wesley Morris, “Latchup in CMOS,” IEEE 03CH37400, 41stAnnual International Reliability Physics Symposium, Dallas, Texas, 2003, © 2003 by IEEE, pp. 76-84.
J. F. Ziegler, et al., “IBM Experiments in Soft Fails in Computer Electronics (1978-1994),” IBM J. Res. Develop., vol. 40, No. 1, Jan. 1996, © 1996 by IBM, pp. 3-18.
Joseph M. Benedetto, “Economy-Class Ion-Defying ICs in Orbit,” reprinted from IEEE Spectrum, vol. 35, No. 3, Mar. 1998, 6 pages.
D. L. Harame, et al., “Design Automation Methodology and rf/analog Modeling for rf CMOS and SiGeBiCMOS Technologies,” IBM J. Res. & Dev., vol. 47, No. 2/3, Mar./May 2003, © 2003 by IMB, pp. 139-175.
Anthony Jordan, “Rad Hard, Space Ready, Case Study: Evolution of A Fab-Independent Radiation-Hardened COTS IC Supplier,” Reprinted from COTS Journal, Nov. 2001, 5 pages.
Rashid Bashir et al., “A Complementary Bipolar Technology Family With A Vertically Integrated PNP for High-Frequency Analog Application,” IEEE Transactions of Electron Devices, vol. 48, No. 11, Nov. 2001, © 2001 by IEEE, pp. 2525-2534.
S. Voldman, et al., “The Influence of Heavily Doped Buried Layer Implants on Electrostatic Discharge (ESD), Latchup, and A Silicon Germanium Heterojunction Bipolar Transistor in A BiCMOS SiGe Technology,” 42ndAnnual Reliability Physics Symposium Proceedings, 2004, Publication Date: Apr. 25-29, 2004, IEEE International, pp. 143-151.
Bourdelle et al., “Evaluation of High Dose, High Energy Boron Implantation into Cz Substrates for Epi-Replacement in CMOS Technology,” IEEE Transactions on Electron Devices, vol. 48, No. 9, Sep. 2001, © 2001 IEEE pp. 2043-2049.
Bourdelle et al., “Epi-Replacement in CMOS Technology by High Dose, High Energy Boron Implantation into Cz Substrates,” Conference on Ion Implantation Technology; Alpbach, AUSTRIA; Sep. 2000, © 2000 IEEE; pp. 312-315.
Keong et al., “Super Latch-up Resistance of High Dose, High Energy Implanted p+Buried Layers,” 1998 International Conference on Ion Implantation Technology Proceedings; vol. 1; Kyoto, JAPAN; © 1999 IEEE; pp. 99-101.
Pech et al., “Extended Defects in Silicon by MeV B++ Implantation in Different 8″ Cz-Si Wafers,” 1998 International Conference on Ion Implantation Technology Proceedings; vol. 2; Kyoto, JAPAN; © 1999 IEEE; pp. 756-759.
Rubin et al, “Effective Gettering of Oxygen by High Dose, High Energy Boron Buried Layers,” 1998 International Conference on Ion Implantation Technology Proceedings; vol. 2; Kyoto, JAPAN; © 1999 IEEE; pp. 1010-1013.
Morris et al., “Buried Layer/Connecting Layer High Energy Implantation for Improved CMOS Latch-Up,” 1996 Proceedings of the 11thInternational Conference on Ion Implantation Technology; Austin, Texas; © 1997 IEEE, pp. 796-799.
Rubin et al., “Process Architectures Using MeV Implanted Blanket Buried Layers for Latch-Up Improvements on Bulk Silicon,” 1996 Proceedings of the 11thInternational Conference on Ion Implantation Technology; Austin, Texas; © 1997 IEEE, pp. 13-16.
Rubin, L.M., et al., “Process Control Issues for Retrogade Well Implants for Narrow n+/p+ Isolation in CMOS,” Proceedings of the 14th International Conference on Ion Implantation Technology, Sep. 22-27, 2002, pp. 17-20.
Morris. W., et al., “Technical and Economic Considerations for Retrograde Well and Channel Implants,” Proceedings of IEEE Conference on Ion Implantation Technology, Sep. 17-22, 2000, pp. 73-76.
Frei, M.R. et al., “Integration of High-Q Inductors in a Latch-up Resistant CMOS Technology,” Proceedings of the International Electron Devices Meeting, Dec. 1999, pp. 757-760.
Parker John M.
Silicon Space Technology Corp.
Smith Matthew
Zagorin O'Brien Graham LLP
LandOfFree
Buried guard ring and radiation hardened isolation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buried guard ring and radiation hardened isolation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buried guard ring and radiation hardened isolation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3855495