Buried-gate-type semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S328000, C257S329000, C257S335000, C257S341000, C257S505000, C257S506000, C257S520000

Reexamination Certificate

active

07038275

ABSTRACT:
An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes106each having a rectangular section are disposed in its plan section. The interval106T between the long sides of the gate electrodes106is made shorter than the interval106S between the short sides thereof. Further, a belt-like contact opening108is provided between the short sides of the gate electrode106, so that P+source region100and N+source region104are in contact with a source electrode. Consequently, the interval106T between the long sides of the gate electrode106can be set up regardless of the width of the contact opening108.

REFERENCES:
patent: 5998837 (1999-12-01), Williams
patent: 6060731 (2000-05-01), Murata et al.
patent: 6194741 (2001-02-01), Kinzer et al.
patent: 6476443 (2002-11-01), Kinzer
patent: 6878989 (2005-04-01), Izumisawa et al.
patent: 2002/0043684 (2002-04-01), Kubo
patent: 2000-58823 (2000-02-01), None
patent: 2002-100770 (2002-04-01), None
European Search Report dated Nov. 3, 2005.

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