Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
1998-04-29
2004-02-24
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S397000
Reexamination Certificate
active
06696746
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor technology, and more particularly to buried conductors within semiconductor devices and structures, and methods for forming such conductors.
BACKGROUND OF THE INVENTION
Semiconductor technology pervades most electronic devices today. Computers, televisions, videocassette recorders, cameras, etc., all use semiconductor integrated circuits to varying degrees. For example, the typical computer includes microprocessors and dedicated controller integrated circuits (i.e., video controllers, audio controllers, etc.), as well as memory, such as dynamic random-access memory.
Traditionally, the semiconductor industry has used a process that requires first building a device or series of devices, and then connecting the devices together with a wiring level or levels above the active-device surfaces. As integrated circuit designs have become more complex, several external wiring planes have been used to connect adjacent devices. As the number of wiring levels grew, the requirement of the vertical connections has significantly reduced the usefulness of the lower levels.
A limited prior art solution is to use a single buried wiring level in the initial phases of semiconductor fabrication. A single buried wiring level overcomes the limitations of using external wiring planes, but is not entirely applicable to current semiconductor technology. For example, stacked chip arrays require more than one wiring level. Therefore, even if a single buried wiring level is used, external wiring planes are still nevertheless required.
For these and other reasons, there is a need for multiple buried wiring levels within a single semiconductor device or structure.
SUMMARY OF THE INVENTION
The above-identified disadvantages, shortcomings and problems are overcome by the present invention, which will be understood by reading and studying the following specification. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be metal, such as tungsten or a tungsten alloy.
The use of a plurality of conductive elements buried within the substrate of a semiconductor structure overcomes limitations found in the prior art. For example, where each conductive element is a separate buried plane, there may be two or more such planes, such that a three-dimensional semiconductor structure may be formed. Three-dimensional structures, as those of ordinary skill within the art can appreciate, have the ability to significantly reduce the average distance from one segment of a large computer processor and associated memory to another, allowing for higher-density semiconductor storage devices and faster processors.
The invention includes semiconductor structures, devices, and methods to form such structures and devices, of varying scope. In addition to the aspects and advantages of the present invention described in this summary, further aspects and advantages of the invention will become apparent by reference to the drawings and by reading the detailed description that follows.
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Farrar Paul A.
Noble Wendell P.
Micro)n Technology, Inc.
Nadav Ori
Schwegman Lundberg Woessner & Kluth P.A.
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