Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-20
2002-10-22
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S338000, C257S344000
Reexamination Certificate
active
06469347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) device and a manufacturing method therefor, and more particularly, to a buried-channel semiconductor device and a manufacturing method therefor.
2. Background Art
Advances in design technology and process technology have enabled manufacture of a highly integrated circuit on which are mounted a plurality of integrated circuits, which would have been manufactured separately. Attempts have been made to increase the degree of integration of a semiconductor circuit simultaneous with an increase in the processing speed of a processing unit, which can be achieved by means of assembling a processing unit into a one-chip CPU. A semiconductor memory device typified by static random access memory (SRAM) or dynamic random access memory (DRAM) and a highly integrated logic circuit (a logic circuit) including a micro-processing unit (MPU) are fabricated into a single chip. To manufacture such an integrated circuit, a plurality of MOS field-effect elements (hereinafter referred to as MOSFETs) whose configurations differ according to their objectives must be fabricated into a single chip.
MOS field-effect elements comprises an nMOSFET (negative Metal Oxide Semiconductor Field-Effect Transistor) which uses electrons as carriers, and a pMOSFET (positive Metal Oxide Semiconductor Field-Effect Transistor) which uses positive holes as carriers. A circuit is constituted by combination of these transistors. At the time of fabrication of these transistors within a single chip, both the gate electrodes of the nMOSFETs and the gate electrodes of the pMOSFETs are doped with n-type impurities in order to simplify manufacturing processes. The nMOSFETs are formed into surface-channel-type transistors, and the pMOSFETs are formed into buried-channel-type transistors, thereby preventing a decrease in migration of positive holes, the degree of which would otherwise be further decreased by means of a vertical electric field developing in the gate electrode. Such a buried-channel-type pMOSFET is described in, for example, Japanese Patent Application Laid-Open No. Hei-1-214169. The publication describes a semiconductor device, which is produced by means of implantation of two or more types of impurities such that the doping level of impurities within a channel region becomes greater toward the surface thereof, as well as a method of manufacturing the semiconductor device.
In association with miniaturization of an element, an electric current, a so-called punch-through current, which cannot be controlled by the gate electrode, occurs in the bottoms of source/drain regions of the element so as to flow from the source region to the drain region. In a semiconductor device described in, for example, Japanese Patent Application Laid-Open No. Hei-2-203566, in order to prevent occurrence of such a punch-through current, a heavily doped region which is equal in conductivity to a semiconductor substrate is formed within the semiconductor substrate at the bottom of the source/drain region. Japanese Patent Application Laid-Open No. Hei-4-192361 describes a semiconductor device, in which, in order to prevent occurrence of the punch-through current, the surface of the semiconductor substrate is formed into a lightly doped region which is of the same conductivity type as the source/drain region.
FIG. 20
is a cross-sectional view showing a conventional semiconductor device. In the drawing, reference numeral
101
designates a p-type semiconductor substrate;
102
designates an isolation oxide film;
103
designates a gate oxide film;
104
designates a gate electrode containing n-type impurities;
1051
designates an n-well;
1052
designates a p-well;
1061
designates a punch-through stopper, layer containing n-type impurities;
1062
designates a punch-through stopper layer containing p-type impurities;
107
designates a counter-doped layer containing p-type impurities;
1081
through
1084
designate p-type source/drain regions;
1091
through
1094
designate n-type source/drain regions;
1010
designates a side-wall spacer;
1011
and
1014
designate interlayer dielectric films; and
1012
and
1013
designate interconnections. The gate electrode
104
of the pMOSFET and the gate electrode
104
of the nMOSFET are doped with n-type impurities. P-type impurities, such as boron, are implanted into the pMOSFET , to thereby form the counter-doped layer
107
and preventing an increase in threshold voltage.
FIG. 21
is a cross-sectional view of a conventional semiconductor device, showing an enlarged view of a pMOS region shown in FIG.
20
. The punch-through stopper layer
1061
is formed so as to prevent occurrence of a punch-through phenomenon at the bottom of any of the p-type source/drain regions
1081
to
1084
(denoted by points “a”). However, if there arises an increase in the doping level of the surface of the semiconductor substrate
1
, the threshold voltage of the pMOS transistor is increased. To prevent such an increase in the threshold voltage, the semiconductor device is formed such that the peak of doping level appears in proximity to the bottom of the source/drain regions
1081
through
1084
. Although a transistor having an LDD structure is illustrated as an example, the same also applies to a transistor which does not have any LDD structure. Further, the punch-through stopper layer
1062
formed in the nMOS region has the same structure as the punch-through stopper layer
1061
.
In association with further miniaturization of an element, the distance between the source/drain regions has become shorter, so that punch-through has become more likely to arise. Occurrence of a punch-through phenomenon is prevented by increasing the doping level of the punch-through stop layer. However, an increase in the doping level of the punch-through stop layer raises a problem of a rise in threshold voltage.
If the doping level of the counter-doped layer
107
is increased in order to prevent an increase in the threshold voltage, the impurities induce a punch-through current by penetrating through the counter-doped layer
107
(denoted by points “b” shown in FIG.
21
).
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the problems described above, and the object of the present invention is to provide a semiconductor device which prevents occurrence of a punch-through phenomenon and an increase in the threshold voltage even when miniaturized, to thereby achieve high performance. The further object of the present invention is to provide a method of manufacturing such semiconductor device.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor region of first conductivity type formed on the primary surface of a semiconductor substrate and surrounded by an isolation dielectric film. Source/drain regions of second conductivity type are formed on the primary surface of the semiconductor region so as to be separated a predetermined distance away from each other. A gate electrode of first conductivity type is formed on the primary surface of the semiconductor region with a gate insulation film interposed therebetween, so as to face a region sandwiched between the source region and the drain region. A first impurity region of first conductivity type is formed in a portion of the semiconductor region sandwiched between the source region and the drain region within the vicinity of the primary surface of the semiconductor region, and has a first concentration peak. A second impurity region of second conductivity type is formed within the region and in the vicinity of the primary surface of the semiconductor region. The second impurity region of second conductivity type has a second concentration peak at a position shallower than the position of the first concentration peak. A third impurity region of second conductivity type is formed within the region and in the vicinity of the primary surface of the semiconductor region. The third impurity re
Oda Hidekazu
Ueno Shuichi
Yamashita Tomohiro
Dickey Thomas L
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Minh Loan
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