Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-13
2004-06-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S300000, C257S392000, C257S403000, C257S532000
Reexamination Certificate
active
06747318
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits (ICs) and the methods for fabricating them on semiconductor substrates. More specifically, the present invention relates to devices having a buried channel fabricated on a semiconductor substrate and methods for fabricating them.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are ubiquitous in products ranging from personal computers to portable digital assistants (“PDAs”) to cellular telephones. As the functional boundaries between different products have gradually blurred, with portable telephones now providing internet access and PDAs also functioning as global positioning system receivers, the complexity of the ICs in these products has increased at a nearly exponential rate. Often, a single IC must operate at high speed, use little power, have a high level of circuit density and, in many cases, also have both analog and digital functions incorporated into it.
As the number of functions performed by these “systems-on-a-chip” has increased, the number of different devices that must be fabricated on the same semiconductor substrate has also increased, such devices including multiple types of transistors and low leakage capacitors. Each different device that must be fabricated on the same IC complicates the already complicated semiconductor processing flow. One particular problem of fabricating so many different devices on the same IC at the same time is that the different devices need gate oxides of different thickness.
Although the formation of oxides, particularly silicon dioxide, in silicon semiconductor processing is well known and technically straightforward, fabricating oxides of different thickness on the same semiconductor wafer during processing is difficult. One known method for fashioning oxides of different thickness is known as “grow-etch-grow.” In this method, a first gate oxide layer is grown on a semiconductor wafer. The wafer is then masked in a known manner and the first layer gate oxide is etched away from certain areas. The mask is then stripped and a second, additional oxide layer is grown on the wafer. The cycle is repeated until the different oxide layers have reached their desired thickness.
For the particular device known as a 1-T random access memory (“RAM”), wherein a capacitor stores an individual bit of data, the capacitors are fabricated using a poly-insulator-poly (“PIP”) process. The PIP method fabricates capacitors by etching an additional trench within the shallow trench isolation (“STI”) region of the wafer. A first polysilicon layer is deposited in the additional trench. A dielectric layer is then formed, followed by as many additional trenches, polysilicon and dielectric layers as necessary. This succession of layers forms the desired capacitor.
Both methods have significant drawbacks. Each oxide growth cycle is charged against the process temperature budget, as oxide growth requires relatively high temperatures that affect concentrations of implanted dopants in other regions of the wafer. Every additional process step increases fabrication costs both directly and indirectly, as manufacturing yield declines with each additional manufacturing step.
Particularly as semiconductor processing technology moves to sub-180 nanometer (nm) technologies, there is a need to create devices on the same wafer with different effective oxide thickness without increasing the number of process steps overall.
SUMMARY OF THE INVENTION
In a first embodiment of the present invention, buried channel NMOS devices are fabricated. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +V
e
with respect to the device's well, a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias as the charge carriers are of the opposite type than the p-well. Under inversion bias, the buried channel silicon region is partially depleted of charge carriers, which effectively adds to the thickness of the gate dielectric layer. A capacitor or transistor fabricated according to this buried channel teaching behaves in a manner electrically equivalent to a capacitor or transistor fabricated with a thicker dielectric.
By using both conventional devices and devices incorporating the buried channel of the present invention on the same IC, effective additional dielectric thickness is obtained without the need to physically grow a thicker dielectric. The thicker dielectric created by the buried channel also reduces the amount of current leakage between the gate electrode and the substrate in capacitors, which is a significant problem when dielectric thickness is less than or equal to about 22 Å. The reduced leakage makes buried channel capacitors very useful for such applications as filter capacitors in phase locked loops (“PLLs”), storage capacitors for 1-transistor RAM (1-T RAM) and voltage stabilizing on-chip capacitors.
PMOS transistors and capacitors can be constructed according to the present invention in a manner similar to that described for NMOS transistors and capacitors by substituting n-type doping for p-type and visa versa. This leads to the fabrication of CMOS devices with multiple effective dielectric thicknesses on the same substrate.
REFERENCES:
patent: 4302764 (1981-11-01), Fang et al.
patent: 5032786 (1991-07-01), Kimura
patent: 5208473 (1993-05-01), Komori et al.
patent: 5523603 (1996-06-01), Fishbein et al.
patent: 5605861 (1997-02-01), Appel
patent: 5616948 (1997-04-01), Pfiester
patent: 5688722 (1997-11-01), Harrington, III
patent: 5767557 (1998-06-01), Kizilyalli
patent: 5998828 (1999-12-01), Oeno et al.
patent: 6066880 (2000-05-01), Kusunoki
patent: 6207510 (2001-03-01), Abeln et al.
patent: 6221703 (2001-04-01), Liu et al.
patent: 6222234 (2001-04-01), Imai
patent: 6245607 (2001-06-01), Tang et al.
patent: 6285052 (2001-09-01), Draper
patent: 6373102 (2002-04-01), Huang
patent: 6436749 (2002-08-01), Tonti et al.
patent: 6462379 (2002-10-01), Higashi et al.
patent: 6555446 (2003-04-01), Unnikrishnan
patent: 6593799 (2003-07-01), De et al.
patent: 2002/0058424 (2002-05-01), Rotondaro
patent: 422129 (1997-09-01), None
patent: 2-280381 (1990-11-01), None
patent: 7-273212 (1995-10-01), None
patent: 7-321220 (1995-12-01), None
patent: 9-321276 (1997-12-01), None
patent: 2001-85533 (2001-03-01), None
Hsiao Tommy
Kapre Ravindra M.
Min Kyungjin
Wang Yanhua
Beyer Weaver & Thomas LLP
Flynn Nathan J.
LSI Logic Corporation
Sefer Ahmed N.
LandOfFree
Buried channel devices and a process for their fabrication... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buried channel devices and a process for their fabrication..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buried channel devices and a process for their fabrication... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3334792