Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-29
2003-09-16
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S403000, C257S407000, C257S412000, C257S616000
Reexamination Certificate
active
06621125
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89109006, filed May 11, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a buried channel device structure. More particularly, the present invention relates to a buried channel device for strengthening the protective capacity of an electrostatic protection circuit.
2. Description of Related Art
Electrostatic discharge is one of the leading causes of damage to an integrated circuit (IC) such as dynamic random access memory (DRAM) and static random access memory (SRAM) during manufacturing and post-manufacture transportation. For example, a person walking on a carpet in an environment with a high relative humidity can generate several hundred to several thousand volts of static electricity. Under exceptionally dry conditions, a voltage of up to ten thousand volts is possible. When the charged body makes contact with a silicon chip, static electricity may discharge irreparably damage the chip. To reduce chip damage due to electrostatic discharge, hard-wired electrostatic discharge circuits are often provided. In other words, an on-chip electrostatic discharge protection circuit is formed between the internal circuit and each bonding pad.
As the gate terminal of a transistor is reduced due to miniaturization, the dual-doped gate has gradually replaced the single doped gate.
FIG. 1A
is a cross-sectional view of a conventional MOSFET having an n-surface channel. In
FIG. 1A
, the MOSFET includes a p-type substrate
10
, a gate oxide layer
18
, a gate terminal
12
above the gate oxide layer
18
and a pair of source/drain terminals
14
and
16
in the substrate
10
. The gate terminal
12
and the source/drain terminals
14
and
16
are formed in two n+ ion implants.
FIG. 1B
is a cross-sectional view of a conventional MOSFET having a p-surface channel. Similarly, in
FIG. 1B
, the MOSFET includes an n-type substrate
20
, a gate oxide layer
28
, a gate terminal
22
above the gate oxide layer
28
and a pair of source/drain terminals
24
and
26
in the substrate
20
. The gate terminal
22
and the source/drain terminals
24
and
26
are formed in two n+ ion implants. In both the n- and p- surface channel MOSFET, an electric current I will flow through the channel close to the gate oxide layer (
18
or
28
) when the MOSFET is in operation.
In general, a surface n-channel or p-channel can effectively improve the short channel effect and can operate with minimal power in CMOS transistor that has a low and symmetrical threshold voltage. However, when the surface channel MOSFET having a dual-doped gate is used in an electrostatic discharge protection circuit, protection capacity is compromised because the operating current flows too close to the gate oxide layer.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a buried channel device for an electrostatic discharge protection circuit such that current flows through a path away from the gate oxide layer and maximizes electrostatic discharge protection.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a buried channel device structure for an electrostatic discharge protection circuit. The buried channel device structure includes a p-doped substrate, a p+ ion-doped region, a first n+ ion-doped region, a second n+ ion-doped region and an n-doped region. The p+ ion-doped region is formed above the p-doped substrate serving as a gate terminal. The first n+ ion-doped region is formed in the p-doped substrate on one side of the p+ ion-doped region serving as a source terminal. The second n+ ion-doped region is formed in the p-doped substrate on the other side of the p+ ion-doped region serving as a drain terminal. The n-doped region is formed under the p+ ion-doped region in the p-doped substrate between the first n+ ion-doped region and the second n+ ion-doped region. Due to the presence of an n-doped region under the p+ ion-doped gate terminal, current flows through a path away from the gate oxide layer. Hence, operation of the electrostatic discharge protection circuit is unaffected.
Similarly, a buried channel device in an n-doped substrate is able to re-direct current through a path away from the gate oxide layer. Hence, operation of the electrostatic discharge protection circuit is also unaffected. The buried channel device structure includes an n-doped substrate, an n+ ion-doped region, a first p+ ion-doped region, a second p+ ion-doped region and a p-doped region. The n+ ion-doped region is formed above the n-doped substrate serving as a gate terminal. The first p+ ion-doped region is formed in the n-doped substrate on one side of the n+ ion-doped region serving as a source terminal. The second p+ ion-doped region is formed in the n-doped substrate on the other side of the n+ ion-doped region serving as a drain terminal. The p-doped region is formed under the n+ ion-doped region in the n-doped substrate between the first p+ ion-doped region and the second p+ ion-doped region.
This invention also provides a method of forming a buried channel device in an electrostatic discharge protection circuit. A polysilicon gate layer is formed on the p-doped substrate of an electrostatic discharge protection circuit. An ion implant is carried out, implanting p+ ions into the polysilicon gate layer. The p+ ion-doped layer is partially etched to form a p+ gate terminal. An n+ ion implant is carried out, implanting n+ ions into the p-doped substrate and the p+ gate terminal. Concentration of the p+ ions is greater than concentration of the n+ ions. Consequently, a first n+ ion-doped region and a second n+ ion-doped region are formed in the p-doped substrate on each side of the p+ gate terminal and an n-doped region is formed in the p-doped substrate under the p+ gate terminal. The first and the second n+ ion-doped region become the source and drain terminal of the buried channel device.
Similarly, the method of forming an n-channel buried channel device in an electrostatic discharge protection circuit is also suitable for forming a p-channel buried channel device. A polysilicon gate layer is formed on the n-doped substrate of an electrostatic discharge protection circuit. An ion implant is carried out, implanting n+ ions into the polysilicon gate layer. The n+ ion-doped layer is partially etched to form an n+ gate terminal. A p+ ion implant is carried out, implanting p+ ions into the n-doped substrate and the n+ gate terminal. Concentration of the n+ ions is greater than concentration of the p+ ions. Consequently, a first p+ ion-doped region and a second p+ ion-doped region are formed in the n-doped substrate on each side of the n+ gate terminal and a p-doped region is formed in the n-doped substrate under the n+ gate terminal. The first and the second p+ ion-doped region become the source and drain terminal of the buried channel device.
REFERENCES:
patent: 5208719 (1993-05-01), Wei
patent: 5742555 (1998-04-01), Marr et al.
patent: 5952701 (1999-09-01), Bulucea et al.
J.C. Patents
United Microelectronics Corp.
Wojciechowicz Edward
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