Buried bit line non-volatile floating gate memory cell with...

Details Buried bit line non-volatile floating gate memory cell with... Buried bit line non-volatile floating gate memory cell with...

2007-12-11

2007-12-11

Rose, Kiesha (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S266000

Reexamination Certificate

active

10797296

ABSTRACT:
A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.

REFERENCES:
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5739567 (1998-04-01), Wong
patent: 6093945 (2000-07-01), Yang
patent: 6103573 (2000-08-01), Harari et al.
patent: 6281545 (2001-08-01), Liang et al.
patent: 6420231 (2002-07-01), Harari et al.
patent: 6426896 (2002-07-01), Chen
patent: 6541815 (2003-04-01), Mandelman et al.
patent: 6597036 (2003-07-01), Lee et al.
patent: 6952034 (2005-10-01), Hu et al.
patent: 2002/0056870 (2002-05-01), Lee et al.
patent: 2002/0163031 (2002-11-01), Lee et al.
IEEE, 2002, entitled “Quantum-well Memory Device (QW/MD) With Extremely Good Charge Retention,” Z. Krivokapic, et al. (4 pages).

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