Buried bit line DRAM cell

Details Buried bit line DRAM cell Buried bit line DRAM cell

1994-11-04

1995-11-21

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257389, H01L 27108, H01L 2976

Patent

active

054689805

ABSTRACT:
Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.

REFERENCES:
patent: 4493057 (1985-01-01), McElroy
patent: 4891747 (1990-01-01), Baglee
patent: 4958318 (1990-09-01), Harari
patent: 4959698 (1990-09-01), Shinichi
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5170234 (1992-12-01), Baglee et al.
patent: 5188975 (1993-02-01), Kojima et al.

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