Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2001-11-01
2004-07-27
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S781000
Reexamination Certificate
active
06768210
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to structure and fabrication methods of wafer-scale devices and their assembly onto wiring boards.
DESCRIPTION OF THE RELATED ART
In their book “Chip Scale Package” (McGraw-Hill, 1999), John H. Lau and Shi-Wei Ricky Lee describe various semiconductor devices and packages of contemporary “chip-scale” families, as they are fabricated by a number of semiconductor companies worldwide. The newest designs and concepts in microelectronics assembly and packaging are aiming for a package with a planar area not substantially greater than the silicon chip itself, or at most 20% larger area. This concept, known as Chip-Scale Package (CSP), is finding particular favor with those electronics industries where the product size is continually shrinking such as cellular communications, pagers, hard disk drivers, laptop computers and medical instrumentation. Most CSP approaches are based on flip-chip assembly with solder bumps or solder balls on the exterior of the package, to interface with system or wiring boards.
A typical flip-chip process calls for solder-compatible contact pads on the circuit surface of the chip, and the deposition of solder bumps or balls thereon. The semiconductor wafers have to be separated into chips before flip-chip attachment to the board. Existing solder bump processes include solder through metal masks, electroplated solder or screen printing a mound of solder paste onto each metallic contact. Typically the solder bumps are reflowed in a chain type furnace. Alternatively, pre-fabricated solder balls may be placed on the chip pads and reflowed in a similar chain type furnace.
The chip-to-be-flipped may then be attached to a second interconnection surface such as an interposer, or alternatively, coupled directly to a printed circuit board (PCB). Attaching the flip-chip to the next interconnect is carried out by aligning the solder bumps or balls on the chip to contact pads on the second level interconnection and then performing a second solder reflow operation. During the reflow, the bumps or balls liquefy and make a bond to the next interconnect level which has pads or traces to receive the solder. Following the solder reflow step, flip-chips often use a polymeric underfill between the chip and the interposer or PCB to alleviate mechanical stress caused by the mismatch in the coefficients of thermal expansion (CTE) between the semiconductor chip, the interposer, if any, and the PCB. Many reliability problems occur due to the stress placed on the solder bumps or balls when the integrated circuit is cycled from hot to cool during operation. The interposers and underfills of the prior art are used to reduce or eliminate the mechanical stress generated by thermal cycling on the solder bumps or balls, but they help little to dissipate thermal energy.
When another set of solder balls on the opposite side of the interposer is employed to complete the bonding process to a PCB, this second set may also be aligned and reflowed for attachment by the end user. When the chip is attached to the board as described, the final consumption of board area is usually not much larger than the area of the chip (about 20% larger). Consequently, this family of products is classified as “chip-scale packages”. However, these devices contribute little to reduce the device height, which is critical in small appliances.
Problems exist with conventional process equipment and flows for chip-scale packages using flip-chip technology. First, a typical solder bumping process is very equipment intensive, resulting in a large capital cost. Evaporation, plating and screening are environmentally unfriendly in that they make use of excess of solder, often containing lead. Both processing and clean-up costs are high in these operations.
Second, the manufacturing of flip-chip assembly can have a long cycle time. Typically, reflows which are carried out in infrared or forced convection ovens have cycle times of 5 minutes or longer. These furnaces are usually very long (>3 m) and massive structures, occupying much space on the assembly floor. Moving parts in such furnaces are a significant source of particulate contamination.
Third, present day assembly of flip-chips is processed in chip form. The assembly process starts after the chip has been diced from the wafer. This type of production strategy causes a disconnect between the wafer fabrication and test plant (“wafer fab”) and the assembly and final test site because the dicing of the wafer must occur outside the clean room environment of a wafer fab. In addition, there are substantial costs in shipping valuable wafers worldwide. After packaging is completed in the assembly sites, the devices must undergo final testing before they can be shipped to the customer. A need thus exists for a packaging method that provides for wafer-scale assembly of integrated circuits, preferably in the clean room facility of the wafer fab itself.
SUMMARY OF THE INVENTION
The present invention describes a semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.
The present invention further discloses several embodiments of semiconductor assemblies in which a chip as described above is bonded to a wiring board which has a plurality of planar, metallurgically bondable terminal pads in a distribution aligned with the distribution of the chip contact pads. The bonding is performed by a technique selected from
Direct welding by metallic interdiffusion;
Attaching by solder paste;
Attaching by conductive adhesive.
In the first embodiment, the chip, with or without the heat spreader, is directly bonded to the board. In the second embodiment, the chip, with or without heat spreader, is first attached to a substrate. In the “ball-grid array” version of this embodiment, the substrate comprises solder balls for the attachment to the wiring board. In the “land-grid-array” version of this embodiment, the device comprises bondable pads for the attachment to the wiring board.
In the third embodiment, the chip, with or without heat spreader, is first attached to a relatively thicker metal patterned in the mirror image of the chip contact pads. This thicker metal, in turn, is the directly bonded to the wiring board. For the third embodiment, as well as for the second embodiments, an encapsulation, for example in protective molding compound, of chip and substrate is preferred. This feature, in turn, provides the condition for assembling extra-thin silicon chip material, a welcome contribution for fabricating low-height chip-scale devices.
The first and the third embodiment can be designed and manufactured as true chip-size devices.
It is a technical advantage of the present invention that a wide variety of materials and techniques can be employed for the proposed metallization and assembly steps.
Other technical advantages of the present invention include a reduction of manufacturing cost, a lead-free assembly solution, improved thermal performance of the package, and improved reliability of the device.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
REFERENCES:
patent: 3737380 (1973-06-01), Bachmeier
p
Koduri Sreenivasan K.
Zuniga-Ortiz Edgar R.
Brady III Wade James
Clark S. V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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