Bumping process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S614000, C438S656000, C438S669000

Reexamination Certificate

active

07091121

ABSTRACT:
A bumping process mainly comprises the following steps. Initially, a wafer having a plurality of bonding pads and a passivation layer, which exposes the bonding pads, is provided. Next, a first dielectric layer is disposed on the wafer so as to form a plurality of first openings and second openings. The first openings and the second openings expose the bonding pads and the passivation layer respectively. Afterward, a patterned first electrically conductive layer is formed on the first dielectric layer, the bonding pads and the passivation layer exposed out of the first dielectric layer through the second openings. Then, a second patterned conductive layer is formed directly on the first patterned conductive layer. Next, a second dielectric layer is formed on the first dielectric layer and the patterned second electrically conductive layer, and exposes portions of the second patterned layer through the second openings so that the exposed portion of the second patterned layer through the second openings are regarded as a plurality of bump pads. Therein, the bump pads are electrically connected to the bonding pads through the patterned first electrically conductive layer and the patterned second electrically conductive layers. Finally, a plurality of bumps are formed on the bump pads and the bumps are then reflowed to be mounted securely on the bump pads.

REFERENCES:
patent: 5162257 (1992-11-01), Yung
patent: 5462638 (1995-10-01), Datta et al.
patent: 5508229 (1996-04-01), Baker
patent: 6013572 (2000-01-01), Hur et al.
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6455408 (2002-09-01), Hwang et al.
patent: 6696357 (2004-02-01), Imai et al.
patent: 6780748 (2004-08-01), Yamaguchi et al.

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