Bumped semiconductor device with alignment features and method f

Details Bumped semiconductor device with alignment features and method f Bumped semiconductor device with alignment features and method f

1996-04-26

1998-03-10

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

257737, 257778, H01L 23544

Patent

active

057265020

ABSTRACT:
A semiconductor device (30) includes a bumped semiconductor die (32) having a plurality of input/output (I/O) bumps (36) and a plurality of alignment bumps (38). Alignment bumps (38) are formed at the same time as I/O bumps (36) and are used by a vision system to properly align die (32) to a mounting substrate (34) for attachment thereto. Because the alignment bumps are smaller than the I/O bumps, the alignment bumps are not damaged during manufacturing operations such as wafer probe, burn-in, or test, and therefore maintain their original shape. The vision system can thus use the alignment bumps to repeatedly and accurately align the die to the mounting substrate, thereby eliminating misalignment caused by damage to the I/O bumps.

REFERENCES:
patent: 5214308 (1993-05-01), Nishiguchi et al.
"Motorola C4 Product Design Manual;" vol. 1: Chip and Wafer Design; ch. 6 (Unit Cell Design); pp. 6-1--6-24 (1993).

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