Bump forming method, presoldering treatment method,...

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Reexamination Certificate

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Reexamination Certificate

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06742701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bump forming method for forming solder bumps that are intended to serve as mechanical and electrical connecting terminals, a method of conducting preliminary treatment before soldering (hereinafter called presoldering treatment) technically associated with said bump forming method, a soldering method grown from said presoldering treatment method, and apparatuses for employing these methods, such as a bump forming apparatus, a presoldering treatment apparatus and a soldering apparatus.
2. Discussion of the Related Art
Conventionally, a bare chip or a similar component having undergone a fine processing is packaged in such a way as to be easily mounted on a printed circuit board. The most typical example of such components are semiconductors. It has heretofore been common practice that an electrode pad portion of a bare chip is connected to an inner lead portion of a lead frame by a wire and sealed with a resin or ceramic material and that an outer lead portion extending to the outside of the chip serves as a mechanical and electrical connecting terminal to be connected to the packaging surface of the printed circuit board.
The rapidly increasing need recently to make electronic devices smaller, thinner, and lighter, as well as faster, has also made it necessary for the electronic components to be smaller and faster. For example, there has been an attempt to reduce the pitch between the leads of a Quad Flat Package (QFP), which is a semiconductor package provided with leads at the four sides of the package, from 0.65 mm to 0.4 mm. In order to cope with further reduction in the size of electronic equipment, vigorous efforts are being made to develop area-array packages of surface mount types.
An area array package is a package provided with electrodes that are arranged in a grid on the bottom of the package. Because of planar arrangement of the electrodes instead of a conventional linear arrangement, an area-array package is compact and provided with numerous pins. The design of connecting terminals for connecting an area array package to a printed circuit board has also changed from those attached to the lead frame to protrusion-shaped terminals (bumps) formed on the electrodes.
A change has also occurred in the wiring in a package, which used to be done with electrical wires; what is becoming necessary is flip chip joining using bumps formed on electrode portions. Such a change has been implemented, because the inductance component and other undesirable characteristics of a wire impair reduction of the operating speed and also cause various problems, such as improper functioning which is caused by simultaneous switching noises.
Examples of area array packages include a ball grid array (BGA), which may be used as a substitute for a QFP, and a chip scale package (CSP), which is reduced to a size nearly the same as a chip.
Furthermore, a part of the flip chip attaching (FCA) technique has already been put into practical use.
Terminals attached to the various electronic elements mentioned above are bump-shaped terminals instead of those of the conventional lead frame type. The most widely used are solder bumps, because they can cope with a batch reflow process, which is a part of the typical conventional procedure for production of a printed circuit board.
With regard to the bump forming technique, several methods have heretofore been offered. Those conventional methods are roughly divided into two categories: those using gold wires and those using solder alloys.
Examples of methods using gold wires include the Stud Bump Bonding (SBB) technique offered by Kyushu Matsushita Electric Co., Ltd. (
IEMT '
93: pp. 362-365, 1993) and the Press Contact technique offered by NEC Corp. (
Mate '
97
Microjoining and Assembly Technology in Electronics
: pp. 15-18, 1997).
Both techniques call for a wire bonder to form gold bumps on the electrode side of a bare chip with a gold wire. With regard to connection of the chip to a substrate, the SBB technique calls for connection using silver paste, while the Press Contact technique calls for maintaining contact between the gold bumps and an electrode pad of the substrate solely by the contraction stress of the underfill resin.
Problems common to these techniques are:
(1) it takes too much time to form bumps, because bumps are formed one by one by studding an electrode pad of a bare chip with a gold wire by using a wire bonder;
(2) using expensive gold increases the cost per bump; and
(3) as a batch reflow process with other surface mount components is impossible, each chip has to be individually mounted on a printed circuit board.
The Press Contact technique presents another problem in that a variance or insufficient accuracy in the height of gold bumps and the degree of surface smoothness of substrates have a considerable influence on obtaining reliable electrical connection, in other words the mounting efficiency, and may therefore present a serious problem in the yield of the product.
Regarding methods of using a solder alloy, a typical method calls for forming a solder bump by placing a solder ball having characteristics within standards on an electrode that is mounted on a bare chip and coated with a fusing agent (hereinafter called “flux”), and then conducting a reflow treatment. Solder balls for BGA are already available.
NEC Corp. has also offered a method of forming solder bumps by using the micropunching technique; this method calls for punching out a solder tape, placing solder pieces on an electrode that is mounted on a bare chip and coated with flux, and then conducting reflow treatment ('95
Japan IEMT Symposium
: pp. 117-120).
Other examples include a solder paste printing method by Hitachi Techno Engineering Co., Ltd. (
Mate '
97
Microjoining and Assembly Technology in Electronics
: pp. 19-22) and a plating method by TOSHIBA CORPORATION (
Mate '
97
Microjoining and Assembly Technology in Electronics
: pp. 23-38).
All of the methods mentioned above call for, in some way or another, placing a solder alloy on an electrode pad and performing reflow to form solder bumps. Flux is always used for the reflow treatment and, thereafter, removed by washing.
In other words, according to any one of the methods of forming solder bumps, flux is indispensable and its washing process is accordingly necessary. Depending on its thoroughness, washing may produce flux residue, which may have a serious influence on the reliability of the finished electronic element.
For this reason, the washing process requires a vigorous cleaner, such as a Freon substitute. In addition to thus necessitating a process that will have an damaging effect on the environment, these methods present a problem of excessively high production costs in their requirement of an expensive facility and disposal of waste liquid.
There have been patent applications relating this field, such as those laid open under Provisional Publication Nos. 293952/1988, 148481/1989 and 500026/1993.
Japanese Patent Provisional Publication No. 293952/1988 describes a method of removing oxides from the surface of solder on an electrode portion by means of hydrogen plasma reduction when the solder is heated and melted in a vacuum.
However, hydrogen reduction damages a passivation film on a bare chip. Furthermore, using hydrogen presents the danger of explosion and requires proper measures to handle the exhaust, resulting in high production costs.
Japanese Patent Provisional Publication No. 148481/1989 describes a method of removing oxides by using argon plasma.
This method, however, is limed to cases of thermal bonding of a flat surface to another flat surface and not applicable to bump formation. Furthermore, a test has proved that treatment using argon plasma is unable to produce good bumps.
The method has another drawback in that the cost of the apparatus is very high, because the initial degree of vacuum in the chamber has to be considerably low: approximately 10
−5
Torr. Furthermo

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