Bump fabrication process

Details Bump fabrication process Bump fabrication process

2003-02-12

2003-12-16

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S614000

Reexamination Certificate

active

06664128

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91103736, filed Mar. 01, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a fabrication process for forming bumps. More particularly, the present invention relates to an etching process for the under bump metallurgy layer in the bump fabrication process.
2. Description of Related Art
At present, the market of multimedia applications rapidly expands. The integrated circuit (IC) packaging needs to be improved following the developing trends of electronic devices such as digitalization, network localization, and user friendliness. In order to meet the above requirements, electronic devices must have multiple functions and high integration and maintain high operating speed, miniaturization, lightweight, and low cost. High-density packages, such as ball grid arrays (BGAs), chip scale packages (CSPs), flip chips, and multi-chip modules (MCMs) have been developed. The integrated circuit packaging density is determined by the degree of numbers of pins per area unit. For high-density IC packaging, the signal transmitting speed increases as the wiring length decreases. Thus, the application of bumps has become the main trend in the high-density packaging.
Referring to the
FIG. 1
, a conventional fabrication process for forming bumps is illustrated in the flow chart. In step
100
, a wafer is provided with a plurality of bonding pads and a protective layer protecting the wafer. In step
102
, an under bump metallurgy (UBM) layer is formed over the wafer. The UBM layer includes an adhesion layer, a barrier layer, and a wetting (solder) layer. In step
104
, after forming the UBM layer, a photoresist layer is formed over the wafer with a plurality of openings, which opening will later on be the formation locations of bumps. In step
106
, solder paste is filled into the openings of the photoresist layer to form bumps. After forming the bumps, in step
108
, the photoresist layer is removed, so that the UBM layer, except the locations covered by the bumps, is exposed. Subsequently, in steps
110
,
112
and
114
, etching is performed to the wetting layer (
110
), the barrier layer (
112
) and the adhesion layer (
114
), respectively.
Materials used in the UBM layer include metals, such as, aluminum, nickel or copper. For UBM layers made of different metal materials, different etchants are selected for the etching process. Nitric acid is usually used for etching the copper layer or the nickel layer, while phosphoric acid of 80 wt. % or more is used for etching the aluminum layer. In the above fabrication process for forming the bump, the UBM layer is removed through several etching steps with different etchants. Moreover, after each etching step, one cleaning step is required to avoid contamination. Therefore, the etching process of the UBM layer is costly and the above fabrication process is time-consuming.
In U.S. Pat. No. 5,508,229, an one-step etching process is proposed for etching the UBM layer over the substrate. The UBM layer is a stacked layer of aluminum
ickel-vanadium/copper. After the bump is formed, an etchant consisting of, phosphoric acid, de-ionized water, acetic acid and hydrogen peroxide is used to remove the aluminum
ickel-vanadium/copper stacked layer at once. Besides, concentrations of phosphoric acid, de-ionized water, acetic acid and hydrogen peroxide are 1% -25%, 63%-8%, 1%-10%, 0.1%-2%, respectively, while the etching temperature is about 70° C. with an etching time of about 90-600 seconds.
From the disclosure of the U.S. Pat. No. 5,508,229, the etching rate is controlled or adjusted by changing the concentrations of the etchant, the etching time or the etching temperature. However, the etching rate can only be adjusted within a very limited range in such way.
SUMMARY OF INVENTION
The present invention provides a bump fabrication process by using a solution containing sulfuric acid as an etchant for etching the nickel-vanadium layer of the under bump metallurgy (UBM) layer.
The present invention provides a bump fabrication process by using a solution containing sulfuric acid as an etchant for removing the nickel-vanadium layer and the copper layer of the under bump metallurgy (UBM) layer altogether.
The present invention provides a bump fabrication process by using a solution containing sulfuric acid as an etchant for removing the stacked aluminum
ickel-vanadium/copper (Al/NiV/Cu) layer of the under bump metallurgy (UBM) layer at once.
The present invention provides a bump fabrication process, in which process the applied voltage controls the etching rate for the thin metal layer.
As embodied and broadly described herein, the present invention provides a bump fabrication process. After forming an under bump metallurgy (UBM) layer and bumps over the substrate, the under bump metallurgy layer that is not covered by the bumps is etched with an etchant. The etchant mainly comprises sulfuric acid and de-ionized water, while the concentration of sulfuric acid is in a range between about 0.5% to about 50% of the etchant. The etchant can etch the nickel-vanadium layer of the UBM layer without damaging the bumps.
The UBM layer includes an adhesion layer, a barrier layer, and a wetting (solder) layer. Materials for forming the UBM layer include aluminum, titanium, titanium-tungsten alloy, chromium, gold, silver, copper and nickel-vanadium alloy, for example.
According to the preferred embodiment, if the bonding pads are aluminum pads, materials of the UBM layer can be, for example, aluminum
ickel-vanadium/copper, titanium
ickel-vanadium/copper, titanium-tungsten
ickel-vanadium/copper or chromium
ickel-vanadium/copper. If the bonding pads are copper pads, materials of the UBM layer can be, for example, titanium
ickel-vanadium/copper, titanium-tungsten
ickel-vanadium/copper or chromium
ickel-vanadium/copper.
For etching the UBM layer, an electrolytic cell containing the etchant is provided with an anode and a cathode. The substrate is arranged on the anode and a voltage is applied between the anode and the cathode. The etching rate of the nickel-vanadium alloy layer is controlled by the electrolysis reaction occurring in the electrolytic cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4922322 (1990-05-01), Mathew
patent: 5108950 (1992-04-01), Wakabayashi et al.
patent: 5508229 (1996-04-01), Baker
patent: 6232212 (2001-05-01), Degani et al.
patent: 6235552 (2001-05-01), Kwon et al.
patent: 6251501 (2001-06-01), Higdon et al.
patent: 6281106 (2001-08-01), Higdon et al.
patent: 6375062 (2002-04-01), Higdon et al.
patent: 6407459 (2002-06-01), Kwon et al.
patent: 6479376 (2002-11-01), Huang et al.

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