Built-in self timing test method and apparatus

Details Built-in self timing test method and apparatus Built-in self timing test method and apparatus

2005-03-15

2005-03-15

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S762010

Reexamination Certificate

active

06867613

ABSTRACT:
A method and apparatus for conducting built-in self-timing tests. In one embodiment, a method for conducting timing tests includes selecting one or more I/O pairs (each I/O pair including a driver and a receiver) into a loop of a ring oscillator, the ring oscillator including an odd number of inverters. The ring oscillator is coupled to a measurement circuit configured to measure delay time in the loop. After initiating operation of the ring oscillator, the delay time through the loop can be measured. Selection circuits may be used to selectively enable or bypass individual I/O pairs in the loop of the ring oscillator. This selective bypassing may allow timing measurements for individual I/O pairs.

REFERENCES:
patent: 5329254 (1994-07-01), Takano
patent: 6759911 (2004-07-01), Gomm et al.
patent: 6760873 (2004-07-01), Hao et al.
patent: 6782498 (2004-08-01), Tanizaki et al.
patent: 6798230 (2004-09-01), Taylor et al.
“Elimination of Traditional Functional Testing of Interface Timings at Intel”, Tripp, et al. ITC International Test Conference,IEEE,Paper 39.2, week of Sep. 29-Oct. 2, 2003, 0-7803-8106-8/03.

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