Built-in self-test system for VLSI circuit chips

Details Built-in self-test system for VLSI circuit chips Built-in self-test system for VLSI circuit chips

1985-11-08

1987-10-20

Smith, Jerry

Excavating

371 15, 324 73R, G01R 3128

Patent

active

047019204

ABSTRACT:
An improved built-in self-test system fabricated on an LSI circuit chip for performing dynamic tests of main logic function operation. The built-in self-test system includes a control register comprising a series of static flip-flops connected for serial test data transfer and for producing test system control signals. An input shift register connected for serial test data transfer with the control register and for parallel test data transfer with the main logic function is formed by a series arrangement of static flip-flops. An output register connected for serial test data transfer with the input register, and for parallel test data transfer with the main logic function, is formed by a series arrangement of static flip-flops. A test clock enable signal is latched by a test clock enable latch, and gated with a system clock signal to produce input and output register clock signals. A test strobe signal is latched by a test strobe latch and strobed by a flip-flop for use as a control register enable signal. The latched test strobe signal and the latched test clock enable signal are gated with the system clock signal for use as a control register clock signal. A test data output multiplexer decodes a test data select signal produced by the control register and supplies test data represented thereby to a test data output pin.

REFERENCES:
patent: 4357703 (1982-11-01), Van Brunt
patent: 4497056 (1985-01-01), Sugamori
patent: 4504784 (1985-03-01), Goel
patent: 4513418 (1985-04-01), Bardell
patent: 4519078 (1985-05-01), Komonytsky
J. J. LeBlanc, "A Built-In Self-Test Technique", IEEE Design & Test, 11/1984 pp. 46-52.

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