Built-in self test for PLL module with on-chip loop filter

Details Built-in self test for PLL module with on-chip loop filter Built-in self test for PLL module with on-chip loop filter

1999-06-22

2003-04-29

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S700000, C714S733000, C375S226000, C375S376000, C324S076480, C324S076530

Reexamination Certificate

active

06557117

ABSTRACT:

FIELD OF THE INVENTION
This application relates generally to integrated circuitry, and more particularly to built in self testing of a phase locked loop module with an on-chip loop filter.
BACKGROUND ART
The on chip integration of a phase locked loop (“PLL”) module and its loop filter has become common place in recent years. However, with the traditional PLL test methods, PLL test vector generation has become a time consuming backend task for many designers as PLLs are designed into more complicated configurations and as technology migrates. A built in self time (BIST) algorithm can dramatically shorten the time that designers spend on test vector generation.
The traditional test,methods have always been developed for PLL modules that have an off-chip loop filters. The following diagram of
FIG. 1
shows the major components for traditional PLL test. The test methodology takes advantage of the fact that the loop filter connection pin can be externally controlled as well as observed. As shown in
FIG. 1
, this pin LP
2
is used as a break point between the two (2) major PLL
105
components, which are the phase detector
110
and the VCO
115
. Each component is tested separately. No close loop test is done.
The traditional PLL test methods require the designer to build hardware around the PLL
105
to enable external access to PLL input and to sample the PLL output frequency. The designer is also required to manually create external input vectors which step through a pre-determined input sequences. On the output side, the designer has to externally interpret the timing of the counter
120
output to determine whether the test has passed or failed.
The traditional tests methodology is too time consuming because it requires manual generation of external input patterns for each PLL module integrated on chip, making the reusing of these vectors out of the question.
The traditional test methodology also does not provide any close-loop test capability.
If the loop filter is integrated on chip, the loop filter connection is no longer accessible for off-chip use. In order to achieve the same testing goal, which is to test the phase detector and the VCO separately, a new test method is needed.
SUMMARY OF THE INVENTION
The present invention concerns an on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.
The basis of the new PLL test methodology is to use built-in self test (BIST) instead of manual test. It is intended that all input sequence for PLL test should be generated automatically and all output results should be interpreted internally. At the end of BIST test, only the pass/fail status flags are available to the designer. In addition, the new method also allows sufficient testing in PLL close loop configuration.


REFERENCES:
patent: 5125107 (1992-06-01), Herold et al.
patent: 5381085 (1995-01-01), Fischer
patent: 5663991 (1997-09-01), Kelkar et al.
patent: 5729151 (1998-03-01), Zoerner et al.
patent: 5889435 (1999-03-01), Smith et al.
patent: 6330681 (2001-12-01), Cote et al.
Press Release—LogicVision and Credence Team to Develop Tester Support for Embedded ATE; Oct. 20, 1998, (3 pgs)—Author(s)—LogicVision Credence Systems Corp.
Press Release—Logicvision Introduces Comprehensive Solution for Core-Based System-On-Chip Testing; Oct. 20, 1998, (3 pgs)—Author(s)—LogicVision Credence Systems Corp.
Advertisement—p11BIST The Chip Level Solution “At-Speed Test of Phase-Locked Loops”. (2 pgs)—Author(s)—LogicVision The Embedded ATE Company.

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