Built-in self-test for analog to digital converter

Details Built-in self-test for analog to digital converter Built-in self-test for analog to digital converter

1999-08-02

2001-12-25

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S155000

Reexamination Certificate

active

06333706

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to built-in self-test circuits for analog to digital converters and, more particularly, to a circuit that uses on-chip signature compression.
BACKGROUND OF THE INVENTION
Analog to digital converters (ADCS) are conventionally used to convert analog signals to digital codes or signals for processing. Dedicated ADC chips can be readily tested in manufacturing by applying a known analog input to the chip and evaluating the digital output. Many current microelectronic circuit chips embed the ADC with processors and other circuits. Embedded ADCs are difficult and time-consuming to test in manufacturing. Access to the digital output data to assess the behavior of the ADC may be difficult or impossible, particularly when testing at speed. The ADC can be tested using static techniques. Digital data is accessed via a serial scan path. However, a 16-bit ADC requires a prohibitive number of scan downloads (from a tester or test time perspective) to verify that the ADC is functional for every digital code.
On the analog input side of ADCS, ramp inputs have traditionally been the preferred technique to stimulate the ADC to exercise all of the digital output codes. This requires either special mixed signal automatic test equipment (ATE) or additional components on the tester to the device under test interface board.
The present invention is directed to solving one or more of the problems discussed above in a novel and simple manner.
SUMMARY OF THE INVENTION
Broadly, there is disclosed herein a built-in self-test (BIST) circuit for an analog to digital converter that uses on-chip signature compression.
Broadly, there is disclosed herein an on-chip analog to digital converter (ADC) test circuit comprising a waveform generator for developing a known arbitrary waveform. Switch means selectively connect the waveform generator to the ADC in a test mode or an internal analog input to the ADC in an operate mode. In the test mode the ADC develops a known sequence of digital codes. A signature register is connected to an output of the ADC for receiving and compressing the sequence of digital codes output from the ADC during the test mode and developing an output representative of the compressed sequence.
In one aspect of the invention, the waveform generator comprises a ramp generator.
In another aspect of the invention the waveform generator comprises an integrator. The integrator has an input connected to receive a clock signal from an external test circuit.
It is a feature of the invention that the signature register comprises a multiple input shift register (MISR) that compresses the sequence of digital codes. The MISR has an input for receiving digital codes from the ADC and updates the compressed sequence of digital codes responsive to a clock signal. The signature register includes a last value register storing a last digital code from the ADC and a comparator compares the last digital code to a current digital code and develops the clock signal if there is a change from the last digital code to the current digital code.
It is another feature of the invention that the signature register can compare the compressed sequence of digital codes to a stored sequence and the output represents the result of the comparison.
It is a further feature of the invention that the signature register includes an output control for transferring the compressed sequence of digital codes to an external test circuit. The output circuit comprises a scan chain or other observation mechanism.
In accordance with another aspect of the invention there is disclosed a built-in self test circuit on an electronic circuit chip including an ADC that converts an analog signal to a corresponding digital code. The circuit includes a waveform generator for developing a known arbitrary analog signal. A switch selectively connects either the waveform generator to an input of the ADC in a test mode, or an internal analog input to the ADC input in an operate mode. In the test mode the ADC develops a known sequence of digital codes. A signature register is connected to an output of the ADC for receiving and compressing the sequence of digital codes output from the ADC during the test mode and developing an output representative of the compressed sequence.
More particularly, the invention solves the problems discussed above by applying an on-chip signature compression to the output of the ADC. The entire transfer function of the ADC in response to the known arbitrary waveform is reduced to the contents of one on-chip signature register. Further, the input to the ADC is generated on-chip with automatic test equipment only supplying an enable or clock signal to the ADC input. This concept may be applied to any monolithic ADC, independent of architecture.
Further features and advantages of the invention will be readily apparent from the specification and from the drawings.


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